W88111AF 데이터 시트보기 (PDF) - Winbond

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W88111AF

ATAPI CD-ROM Decoder & Controller

Winbond 

W88111AF/W88112F

ATAPI CD-ROM Decoder & Controller

This specification is subject to change without notice.

Bit 4: HCIb - Host Command Interrupt Flag

Preliminary/Confidential

This bit is activated by the following events:

• Host issues ATAPI Soft Reset Command, if ARSTIEN(2Fh.1) is enabled

• Host issues command to a non-exist slave drive, if SHIEN(2Eh.2) is enabled

• Host issues Execute Drive Diagnostics Command, if HIIEN(2Eh.7) is enabled

• ATAC(2Fh.6) becomes active-high, if HIIEN(2Eh.7) is enabled

• Host set bit SRST in ATAPI Device Control Register, if HIIEN(2Eh.7) is enabled

Bit 3: TBSYb - Transfer Busy Flag

This bit becomes active-low when the data transfer to host is triggered by the following events:

• Writing any value to register THTRG(06h)

• Setting bit ADTT(17h.2) high

After host reads the last byte to be transferred, TBSYb is deactivated.

Bit 2: MBTIb - Multi-Block Transfer Interrupt Flag

This bit is activated by the following events:

• RPINT(30h.3) becomes active-high while RPIEN(2Ah.5) is enabled

• MBTI(30h.4) becomes active-high while MBKIEN(13h.2) is enabled

The microprocessor can read register MISS2(30h) to tell which event occurs.

Bit 1: DFRDYb - Data FIFO Ready

After data transfer is triggered, the 8-byte Data FIFO is automatically filled. This bit is used to

indicate that the Data FIFO is ready to be read by the host.

Bit 0: SCIb - Subcode Interrupt Flag

If SCIEN(2Ch.4) is enabled, this bit becomes active-low when one of the following events occurs:

• ISS(22h.0) becomes active-high

• NESBK(22h.1) becomes active-high

• MSS(22h.2) becomes active-high

When Subcode Interrupt is activated, the microprocessor can read register SUBSTA(22h) to

determine the reason of interrupt. Writing register SCIACK(22h) deactivates Subcode Interrupt.

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Publication Release Date: Aug, 1996

Preliminary/ Confidential Revision A0.1

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