SST49LF020A 데이터 시트보기 (PDF) - Silicon Storage Technology

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SST49LF020A

2 Mbit LPC Flash

Silicon Storage Technology 

2 Mbit LPC Flash

SST49LF020A

Data Sheet

TABLE 6: LPC Write Cycle

Clock

Cycle

1

Field

Name

START

Field Contents

LAD[3:0]1

0000

LAD[3:0]

Direction

IN

2

CYCTYPE +

011X

IN

DIR

3-10

ADDRESS

YYYY

IN

11

DATA

ZZZZ

IN

12

DATA

ZZZZ

IN

13

TAR0

1111

IN then Float

14

TAR1

1111 (float)

Float then OUT

15

SYNC

0000

OUT

16

TAR0

1111

OUT then Float

17

TAR1

1111 (float)

Float then IN

1. Field contents are valid on the rising edge of the present clock cycle.

Comments

LFRAME# must be active (low) for the part to respond.

Only the last start field (before LFRAME# transitions

high) should be recognized.

Indicates the type of cycle. Bits 3:2 must be “01b” for

memory cycle. Bit 1 indicates the type of transfer “1”

for Write. Bit 0 is reserved.

Address Phase for Memory Cycle. LPC protocol sup-

ports a 32-bit address phase. YYYY is one nibble of

the entire address. Addresses are transferred most-

significant nibble first. See Table 3 for address bits def-

inition and Table 4 for valid memory address range.

This field is the least-significant nibble of the data byte.

This field is the most-significant nibble of the data byte.

In this clock cycle, the host has driven the bus to all ‘1’s

and then floats the bus. This is the first part of the bus

“turnaround cycle.”

The SST49LF020A takes control of the bus during this

cycle.

The SST49LF020A outputs the values 0000, indicat-

ing that it has received data or a flash command.

In this clock cycle, the SST49LF020A has driven the

bus to all ‘1’s and then floats the bus. This is the first

part of the bus “turnaround cycle.”

Host resumes control of the bus during this cycle.

T6.0 1206

CE#

LCLK

LFRAME#

LAD[3:0]

CYCTYPE

Start

+

DIR

Address

0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4]

1 Clock 1 Clock

Load Address in 8 Clocks

Data Data TAR0 TAR1 Sync

A[3:0] D[3:0] D[7:4] 1111b Tri-State 0000b

Load Data in 2 Clocks 2 Clocks 1 Clock

TAR

1206 F07.0

FIGURE 6: LPC Write Cycle Waveform

©2006 Silicon Storage Technology, Inc.

13

S71206-08-000

5/06

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