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SST49LF020A

2 Mbit LPC Flash

Silicon Storage Technology 

Data Sheet

Write Operation Status Detection

The SST49LF020A devices provide two software means to

detect the completion of a Write (Program or Erase) cycle,

in order to optimize the system Write cycle time. The soft-

ware detection includes two status bits: Data# Polling D[7]

and Toggle Bit D[6]. The End-of-Write detection mode is

enabled after the rising edge of WE# which initiates the

internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchro-

nous with the system; therefore, either a Data# Polling or

Toggle Bit read may be simultaneous with the completion

of the Write cycle. If this occurs, the system may possibly

get an erroneous result, i.e., valid data may appear to con-

flict with either D[7] or D[6]. In order to prevent spurious

rejection, if an erroneous result occurs, the software routine

should include a loop to read the accessed location an

additional two (2) times. If both reads are valid, then the

device has completed the Write cycle, otherwise the rejec-

tion is valid.

Data# Polling (DQ7)

When the SST49LF020A device is in the internal Program

operation, any attempt to read DQ7 will produce the com-

plement of the true data. Once the Program operation is

completed, DQ7 will produce true data. Note that even

2 Mbit LPC Flash

SST49LF020A

though DQ7 may have valid data immediately following the

completion of an internal Write operation, the remaining

data outputs may still be invalid: valid data on the entire

data bus will appear in subsequent successive Read

cycles after an interval of 1 µs. During internal Erase opera-

tion, any attempt to read DQ7 will produce a ‘0’. Once the

internal Erase operation is completed, DQ7 will produce a

‘1’. The Data# Polling is valid after the rising edge of fourth

WE# pulse for Program operation. For Sector-, Block-, or

Chip-Erase, the Data# Polling is valid after the rising edge

of sixth WE# pulse. See Figure 20 for Data# Polling timing

diagram and Figure 35 for a flowchart. Proper status will

not be given using Data# Polling if the address is in the

invalid range.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alternating 0s

and 1s, i.e., toggling between 0 and 1. When the internal

Program or Erase operation is completed, the toggling will

stop. The device is then ready for the next operation. The

Toggle Bit is valid after the rising edge of fourth WE# pulse

for Program operation. For Sector-, Block-, or Chip-Erase,

the Toggle Bit is valid after the rising edge of sixth WE#

pulse. See Figure 21 for Toggle Bit timing diagram and Fig-

ure 35 for a flowchart.

TABLE 10: Operation Modes Selection (PP Mode)

Mode

Read

Program

Erase

RST#

VIH

VIH

VIH

OE#

VIL

VIH

VIH

WE#

VIH

VIL

VIL

Reset

VIL

X

X

Write Inhibit

VIH

VIL

X

X

X

VIH

Product Identification

VIH

VIL

VIH

1. X can be VIL or VIH, but no other value.

2. Device ID = 52H for SST49LF020A

DQ

DOUT

DIN

X1

High Z

High Z/DOUT

High Z/DOUT

Manufacturer’s ID (BFH)

Device ID2

Address

AIN

AIN

Sector or Block address,

XXH for Chip-Erase

X

X

X

See Table 11

T10.2 1206

©2006 Silicon Storage Technology, Inc.

18

S71206-08-000

5/06

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