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SST49LF020A Datasheet PDF : 50 Pages
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2 Mbit LPC Flash
SST49LF020A
Multiple Device Selection
Multiple LPC flash devices may be strapped to increase
memory densities in a system. The four ID pins, ID[3:0],
allow up to 16 devices to be attached to the same bus by
using different ID strapping in a system. BIOS support, bus
loading, or the attaching bridge may limit this number. The
boot device must have an ID of 0 (determined by ID[3:0]);
subsequent devices use incremental numbering. Equal
density must be used with multiple devices.
When used as a boot device, ID[3:0] must be strapped as
0000; all subsequent devices should use a sequential up-
count strapping (i.e. 0001, 0010, 0011, etc.). With the hard-
ware strapping, ID information is included in every LPC
address memory cycle. The ID bits in the address field are
inverse of the hardware strapping. The address bits
[A21:A18] are used to select the device with proper IDs. See
Table 7 for IDs. The SST49LF020A will compare these bits
with ID[3:0]’s strapping values. If there is a mismatch, the
device will ignore the reminder of the cycle.
TABLE 7: Multiple Device Selection
Configuration
Hardware
Strapping Address Bits Decoding
Device #
0 (Boot device)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ID[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
A21 A20 A19 A18
1
1
1
1
1
1
1
0
1
1
0
1
1
1
0
0
1
0
1
1
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
T7.2 1206
Data Sheet
Registers
There are two registers available on the SST49LF020A,
the General Purpose Inputs Registers (GPI_REG) and the
JEDEC ID Registers. Since multiple LPC memory devices
may be used to increase memory densities, these registers
appear at its respective address location in the 4 GByte
system memory map. Unused register locations will read
as 00H. Any attempt to read registers during internal Write
operation will respond as “Write operation status detection”
(Data# Polling or Toggle Bit). Any attempt to write any reg-
isters during internal Write operation will be ignored. Table
9 lists GPI_REG and JEDEC ID address locations for
SST49LF020A with its respective device strapping.
TABLE 8: General Purpose Inputs Register
Pin #
Bit Function
7:5 Reserved
4 GPI[4]
Reads status of general
purpose input pin
3 GPI[3]
Reads status of general
purpose input pin
2 GPI[2]
Reads status of general
purpose input pin
1 GPI[1]
Reads status of general
purpose input pin
0 GPI[0]
Reads status of general
purpose input pin
32-PLCC
-
30
32-TSOP
-
6
3
11
4
12
5
13
6
14
T8.0 1206
©2006 Silicon Storage Technology, Inc.
15
S71206-08-000
5/06
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