CXD1186CR 데이터 시트보기 (PDF) - Sony Semiconductor

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CXD1186CR

CD-ROM Decoder

Sony Semiconductor 

CXD1186CQ/CR

Description of Function

1. Pin description

Below is a description of pins by function.

1.1 CD player interface (4 pins)

(1) DATA (input)

Serial data from CIRC LSI (digital signal processing LSI for CD)

(2) BCLK (input)

Bit clock. Clock for DATA Strobe.

(3) LRCK (input)

LR clock. Indicates LCH and RCH of DATA input.

(4) C2PO (positive logic input)

C2 pointer signal from CIRC. Indicates an error is included in the DATA input.

Interface mode with the CD player is controlled at DRVIF register.

1.2 Buffer memory interface (27 pins)

(1) XMWR (memory write, negative logic output)

Data write strobe signal of the buffer memory.

(2) XMOE (memory output enable, negative logic output)

Data read strobe signal of the buffer memory.

(3) BA0 to 15 (Buffer memory address, output)

Address signal of the buffer memory.

(4) BDB0 to 7 (Buffer data bus, I/O)

Data bus signal of the buffer memory.

(5) BDBP (Buffer data bus, I/O)

Buffer memory data bus signal for error pointer.

1.3 CPU interface (16 pins)

(1) XWR (CPU write, negative logic input)

Write strobe signal of the CPU register.

(2) XRD (CPU read, negative logic input)

Read out strobe signal of the CPU register.

(3) XCS (CPU chip select, negative logic input)

Chip select negative logic signal from the CPU.

(4) A0 to 3 (CPU address, input)

Address signal for the CPU selection of the IC internal register.

(5) DB0 to 7 (CPU data bus, I/O)

CPU data bus signal.

(6) INT (CPU interrupt, output)

Interrupt request output to the CPU. This pin polarity is controlled at the CONFIG register.

1.4 Host interface (19 pins)

(1) HMDS (Host mode select, input)

Signal for the host mode selection. This pin is pulled down inside the IC by means of a resistor at a

standard 50 kΩ.

“L” or open : connected to Intel 80 type host Bus.

“H”

: connected to SCSI controller IC.

(2) HDRQ/XSAC (Host data request/SCSI acknowledge, output)

When HMDS is at “L”, DMA data request positive logic signal to host.

When HMDS is at “H”, DMA acknowledge negative logic signal to SCSI control IC.

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