CXD1186CR 데이터 시트보기 (PDF) - Sony Semiconductor
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CXD1186CR Datasheet PDF : 46 Pages
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CXD1186CQ/CR
2.1.3 DMA Control (DMACTL) register
bit0 : HSRC (Host Source)
“H” ; Data is transferred from the host to the buffer memory.
“L” ; Data is transferred from the buffer memory to the host.
bit1 : HDMAEN (HOST DMA Enable)
“H” ; DMA of the host port is enabled.
“L” ; DMA of the host port is prohibited.
bit2 : ENXTC (Enable XTC)
“H” ; DMA completion of the host port through XTC pin input is enabled.
“L” ; DMA completion of the host port through XTC pin input is disabled.
bit3 : ENHXFRC (Enable XHFRC)
“H” ; DMA completion of the host port through HXFRC is enabled.
“L” ; DMA completion of the host port through HXFRC is disabled.
bit4 : ADMAEN (ADP DMA Enable)
“H” ; DMA of the audio processor port is enabled.
“L” ; DMA of the audio processor port is prohibited.
Also, prohibits turning HDMAEN and ADMAEN simultaneously to “H”.
bit5 : CSRC (CPU Source)
“H” ; Data is transferred from the CPU to the buffer memory.
“L” ; Data is transferred from the buffer memory to the CPU.
bit6 : CDMAEN (CPU DMA Enable)
“H” ; DMA of the CPU port is enable.
“L” ; DMA of the CPU port is prohibited.
bit7 : RESERVED
Unused, Keep set to “L”.
2.1.4 Configuration (CONFIG) register
bit0 : RESERVED
Unused, Keep set to “L”.
bits1 and 2 : SDMACYC1, 0 (SCSI DMA CYCLE)
DMA transfer between this IC, SCSI control IC and ADPCM processor is executed in the
following cycle.
SDMACYC1
0
“L”
“L”
3 cycle.
“L”
“H”
4 cycle.
“H”
“X”
5 cycle.
bit3 : SBSCTL (SCSI Bus Control)
Setting this bit to “H” forces XHWR, XHRD, HDB0 to 7 and HDBP into high impedance condition.
bit4 : CINTPOSI (CPU Interrupt Positive)
“H” ; INT pin turns to High active.
“L” ; INT pin turns to Low active.
bit5 : 9 BITRAM
“H” ; When a 9 bit/word RAM is connected, this bit is turned to “H”.
“L” ; When a 8 bit/word RAM is connected, this bit is turned to “L”.
bits6 and 7 : RESERVED
Unused, Keep set to “L”.
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