TJA1051(2017) 데이터 시트보기 (PDF) - NXP Semiconductors.
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TJA1051 Datasheet PDF : 25 Pages
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NXP Semiconductors
TJA1051
High-speed CAN transceiver
Table 7. Static characteristics …continued
Tvj = 40 C to +150 C; VCC = 4.5 V to 5.5 V; VIO = 2.8 V to 5.5 V[1]; RL = 60 unless specified otherwise; All voltages are
defined with respect to ground; Positive currents flow into the IC[2].
Symbol Parameter
Conditions
Min
Typ Max
Unit
Ci(dif)
differential input capacitance
Temperature protection
[6] -
-
10
pF
Tj(sd)
shutdown junction
temperature
[6] -
190 -
C
[1] Only TJA1051T/3 and TJA1051TK/3 have a VIO pin. In transceivers without a VIO pin, the VIO input is internally connected to VCC.
[2] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[3] VIO = VCC for the non-VIO product variants TJA1051T(/E)
[4] Only TJA1051T/E has an EN pin.
[5] Maximum value assumes VCC < VIO; if VCC > VIO, the maximum value will be VCC + 0.3 V.
[6] Not tested in production; guaranteed by design.
[7] The test circuit used to measure the bus output voltage symmetry (which includes CSPLIT) is shown in Figure 8.
11. Dynamic characteristics
Table 8. Dynamic characteristics
Tvj = 40 C to +150 C; VCC = 4.5 V to 5.5 V; VIO = 2.8 V to 5.5 V[1]; RL = 60 unless specified otherwise. All voltages are
defined with respect to ground. Positive currents flow into the IC.[2]
Symbol
Parameter
Conditions
Min Typ Max Unit
Transceiver timing; pins CANH, CANL, TXD and RXD; see Figure 7 and Figure 3
td(TXD-busdom)
td(TXD-busrec)
td(busdom-RXD)
td(busrec-RXD)
td(TXDL-RXDL)
delay time from TXD to bus dominant
delay time from TXD to bus recessive
delay time from bus dominant to RXD
delay time from bus recessive to RXD
delay time from TXD LOW to RXD LOW
Normal mode
Normal mode
Normal/Silent mode
Normal/Silent mode
Normal mode: versions
with VIO pin
Normal mode: other
versions
-
65 -
ns
-
90 -
ns
-
60 -
ns
-
65 -
ns
40 -
250
ns
40 -
220
ns
td(TXDH-RXDH)
delay time from TXD HIGH to RXD HIGH
Normal mode: versions
with VIO pin
Normal mode: other
versions
40 -
250
ns
40 -
220
ns
tbit(bus)
transmitted recessive bit width
tbit(RXD)
bit time on pin RXD
trec
receiver timing symmetry
tto(dom)TXD
TXD dominant time-out time
tbit(TXD) = 500 ns
[3] 435 -
530
ns
tbit(TXD) = 200 ns
[3] 155 -
210
ns
tbit(TXD) = 500 ns
[3] 400 -
550
ns
tbit(TXD) = 200 ns
[3] 120 -
220
ns
tbit(TXD) = 500 ns
65 -
+40
ns
tbit(TXD) = 200 ns
45 -
+15
ns
VTXD = 0 V; Normal mode [4] 0.3 1
5
ms
[1] Only TJA1051T/3 and TJA1051TK/3 have a VIO pin. In transceivers without a VIO pin, the VIO input is internally connected to VCC.
[2] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
TJA1051
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 28 November 2017
© NXP N.V. 2017. All rights reserved.
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