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TTRN012G5

TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer

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Preliminary Data Sheet

August 2000

TTRN012G5 and TTRN012G7

Clock Synthesizer, 16:1 Data Multiplexer

Functional Overview

The Lucent Technologies Microelectronics Group TTRN012G5 operates at the OC-48/STM-16 data rate of

2.5 Gbits/s.* The TTRN012G7 device operates at either 2.5 Gbits/s or the RS FEC OC-48/STM-16 data rate of

2.7 Gbits/s. The device performs the clock synthesis and 16:1 data multiplexing operations required to support

2.5 Gbits/s applications compliant with Telcordia Technologies and ITU standards. Parallel 155 Mbits/s data is

clocked into an input register and checked for valid parity. Both clockless data transfer and contra-directional clock-

ing modes are supported. The data is then multiplexed into a 2.5 Gbits/s serial stream and output buffered for inter-

facing to a laser driver. A 2.5 GHz clock is synthesized from a reference clock and is used to retime the serial data.

The 2.5 GHz clock is optionally available as an output. The serial data stream polarity can be inverted under pin

control to make interfacing easier.

Clock Synthesizer Operation

The clock synthesizer uses a PLL to synthesize a 2.5 GHz clock from a reference frequency. A 155 MHz clock

derived from the 2.5 GHz synthesized clock may be used to clock in the parallel data.

Clock Synthesizer Loop Filter

A typical loop filter that provides adequate damping for less than 0.1 dB of jitter peaking is shown in Figure 3. Con-

nect the filter components and also connect LFP to VCP and connect LFN to VCN. The component values can be

varied to adjust the loop dynamic response (see Table 5).

Table 5. Clock Synthesizer Loop Filter Component Values

Components

C1*

C2, C3

R1

Values for 2 MHz Loop Bandwidth

0.10 µF ± 10%

10 pF ± 20%

680 Ω ± 5%

* Capacitor C1 should be either ceramic or nonpolar.

LFP/VCP

LFN/VCN

C1 R1

C2

C3

Figure 3. Clock Synthesizer Loop Filter Components

5-8061(F)

Clock Synthesizer Settling Time

The clock synthesizer will acquire phase/frequency lock after a valid reference clock is applied to the REFCLKP/N

input pins. The actual time to acquire lock is a function of the loop bandwidth selected. The loop will acquire lock

within 5 ms when using the external loop bandwidth components corresponding to 2 MHz.

Loss of Lock Indicator (LCKLOSSN)

The LCKLOSSN pin indicates (active-low) when the clock synthesizer has exceeded phase-lock limits with the

incoming REFCLKP/N phase. The lock detect function compares the phases of the input 155 MHz clock at the

REFCLKP/N pins with the internally generated 155 MHz output clock at the CK155P/N pins. When the phase dif-

ference in the two signals is close to zero as determined by a second internal phase detector and filter, the lock

detect signal LCKLOSSN is set to the logic high state. When the phase difference between the two signals is

changing with time at a rate exceeding the filter's cutoff frequency, the device is declared out of lock and lock

detect signal LCKLOSSN is set to a logic low. If a set of highly damped phase-locked loop parameters is chosen

for the device, LCKLOSSN may exhibit more than one positive edge transition during the acquisition process

before a steady logic high state is achieved.

* The OC-48/STM-16 data rate of 2.48832 Gbits/s is typically approximated as 2.5 Gbits/s in this document when referring to the application

rate. The RS FEC OC-48/STM-16 data rate is 2.66606 Gbits/s and is approximated as 2.7 Gbits/s in this document. Similarly, the OC-3/

STM-1 data rate of 155.52 Mbits/s is typically approximated as 155 Mbits/s, and the RS FEC OC-3/STM-1 data rate of 166.62 Mbits/s is

approximated as 166 Mbits/s. The exact frequencies are used only when necessary for clarity.

Lucent Technologies Inc.

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