AD9857/PCB(Rev0) 데이터 시트보기 (PDF) - Analog Devices
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AD9857/PCB Datasheet PDF : 31 Pages
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AD9857
Parameter
Temp
Test
AD9857
Level Min Typ Max
Unit
SPURIOUS POWER (Off Channel, Measured in
Equivalent Bandwidth), Output Attenuated 18 dB
Relative to Full Scale
6.4 MHz Bandwidth
25°C
IV
–51
dBc
3.2 MHz Bandwidth
25°C
IV
–54
dBc
1.6 MHz Bandwidth
25°C
IV
–56
dBc
0.8 MHz Bandwidth
25°C
IV
–59
dBc
0.4 MHz Bandwidth
25°C
IV
–62
dBc
0.2 MHz Bandwidth
25°C
IV
–63
dBc
TIMING CHARACTERISTICS
Serial Control Bus
Maximum Frequency
Minimum Clock Pulsewidth Low (tPWL)
Minimum Clock Pulsewidth High (tPWH)
Maximum Clock Rise/Fall Time
Minimum Data Setup Time (tDS)
Minimum Data Hold Time (tDH)
Maximum Data Valid Time (tDV)
Wake-Up Time1
Minimum RESET Pulsewidth High (tRH)
Minimum CS Setup Time
25°C
I
25°C
I
25°C
I
25°C
I
25°C
I
25°C
I
25°C
I
25°C
I
25°C
I
25°C
I
10
30
30
1
30
0
35
1
5
40
MHz
ns
ns
ms
ns
ns
ns
ms
SYSCLK2 Cycles
ns
CMOS LOGIC INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
25°C
I
2.0
V
25°C
I
0.8
V
25°C
I
5
µA
25°C
I
5
µA
25°C
V
3
pF
CMOS LOGIC OUTPUTS (1 mA LOAD)
Logic “1” Voltage
Logic “0” Voltage
25°C
I
25°C
I
POWER SUPPLY VS CURRENT3 (All Power Specs
at VDD = 3.3 V, 25°C, REFCLK = 200 MHz)
Full Operating Conditions
25°C
I
160 MHz Clock (×16)
25°C
I
120 MHz Clock (×12)
25°C
I
Burst Operation (25%)
25°C
I
Single-Tone Mode
25°C
I
Power-Down Mode
25°C
I
Full-Sleep Mode
25°C
I
2.7
mA
0.4
mA
615
mA
515
mA
400
mA
450
mA
310
mA
80
mA
13.5
mA
NOTES
1Wake-Up Time refers to recovery from Full Sleep Mode. The longest time required is for the Reference Clock Multiplier PLL to lock up (if it is being used). The
Wake-Up Time assumes that there is no capacitor on DAC_BP, and that the recommended PLL loop filter values are used. The state of the Reference Clock Multi-
plier lock can be determined by observing the signal on the PLL_LOCK pin.
2SYSCLK refers to the actual clock frequency used on-chip by the AD9857. If the Reference Clock Multiplier is used to multiply the external reference frequency, the
SYSCLK frequency is the external frequency multiplied by the Reference Clock Multiplier multiplication factor. If the Reference Clock Multiplier is not
used, the SYSCLK frequency is the same as the external REFCLK frequency.
3CIC = 2, INV SINC ON, FTW = 40%, PLL OFF, Auto Power-Down Between Burst On, TxENABLE Duty Cycle = 25%.
Specifications subject to change without notice.
REV. 0
–3–
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