AD9857/PCB(Rev0) 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
제조사
AD9857/PCB Datasheet PDF : 31 Pages
| |||
Pin No.
20–14, 7–1
Mnemonic
D0–D6, D7–D13
8–10, 31–33, 73–75
11–13, 28–30, 70–72,
76–78
21
DVDD
DGND
PS1
22
PS0
23
CS
24
SCLK
25
SDIO
26
SDO
27
SYNCIO
34, 41, 51, 52, 57
35, 37, 38, 43, 48,
54, 58, 64
36, 39, 40, 42, 44, 47,
53, 56, 59, 61, 65
45
46
49
50
55
60
NC
AVDD
AGND
IOUT
IOUT
DAC_BP
DAC_RSET
PLL_FILTER
DIFFCLKEN
62
REFCLK
63
REFCLK
66
DPD
67
RESET
68
PLL_LOCK
69
CIC_OVRFL
79
PDCLK/FUD
80
REV. 0
TxENABLE
AD9857
PIN FUNCTION DESCRIPTIONS
I/O Pin Function
I
14-Bit Parallel Data Bus for I and Q Data. The required numeric format is two’s
complement with D13 as the sign bit and D12–D0 as the magnitude bits.
Alternating 14-bit words are demultiplexed onto the I and Q data pathways
(except when operating in the Interpolating DAC Mode, in which case every
word is routed onto the I data path). When the TxENABLE pin is asserted high,
the next accepted word is presumed to be I data, the next Q data, and so forth.
3.3 V Digital Power Pin(s).
Digital Ground Pin(s).
I
Profile Select Pin 1. The LSB of the two profile select pins. In conjunction
with PS0, selects one of four profile configurations.
I
Profile Select Pin 0. The MSB of the two profile select pins. In conjunction
with P1, selects one of four profile configurations.
I
Serial Port Chip Select Pin. An active low signal that allows multiple devices
to operate on a single serial bus.
I
Serial Port Data Clock Pin. The serial data CLOCK for the Serial Port.
I/O Serial Port Input/Output Data Pin. Bidirectional serial DATA pin for the Serial
Port. This pin can be programmed to operate as a serial input only pin, via a
control register bit 00h<7>. The default state is bidirectional.
O
Serial Port Output Data Pin. This pin serves as the serial data output pin when the
SDIO pin is configured for serial input only mode. The default state is three-state.
I
Serial Port Synchronization Pin. Synchronizes the serial port without affecting
the programmable register contents. This is an active high input that aborts
the current serial communication cycle.
No Connect.
3.3 V Analog Power Pin(s).
Analog Ground Pin(s).
O
DAC Output Pin. Normal DAC output current (analog).
O
DAC Complementary Output Pin. Complementary DAC output current (analog).
DAC Reference Bypass. Normally not used.
I
DAC Current Set Pin. Sets DAC reference current
O
PLL Filter. R-C network for PLL Filter.
I
Clock Mode Select Pin. A logic high on this pin selects DIFFERENTIAL
REFCLK input mode. A logic low selects the SINGLE-ENDED REFCLK
input mode.
I
Reference Clock Pin. In single-ended Clock Mode, this pin is the Reference
Clock input. In differential Clock Mode, this pin is the positive clock input.
I
Inverted Reference Clock Pin. In differential Clock Mode, this pin is the
negative clock input.
I
Digital Power-Down Pin. Assertion of this pin shuts down the digital sections of
the device to conserve power. However, if selected, the PLL remains operational.
I
Hardware RESET Pin. An active high input that forces the device into a
predefined state.
O
PLL Lock Pin. Active high output signifying, in real time, when PLL is in
“lock” state.
O
CIC Overflow Pin. Activity on this pin indicates that the CIC filters are in
“overflow” state. This pin is normally “low” unless a CIC overflow occurs.
I/O Parallel Data Clock/Frequency Update Pin. When not in Single-Tone Mode, this
pin is an output signal that should be used as a clock to synchronize the acceptance
of the 14-bit parallel data words on Pins D13–D0. In Single-Tone Mode, this pin is
an input signal that synchronizes the transfer of a changed frequency tuning word
(FTW) in the active profile (PSx) to the accumulator (FUD = Frequency Update
signal). When profiles are changed by means of the PS–PS1 pins, the FUD does
not have to be asserted to make the FTW active.
I
When TxENABLE is asserted, the device processes the data through the I and Q
data pathways; otherwise 0s are internally substituted for the I and Q data entering
the signal path. The first data word accepted when the TxENABLE is asserted
high is treated as I data, the next data word is Q data, and so forth.
–5–
-
Share Link: 