CDP68HC68T1(1997) 데이터 시트보기 (PDF) - Intersil

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CDP68HC68T1
(Rev.:1997)

CMOS Serial Real-Time Clock With RAM and Power Sense/Control

Intersil 

System Diagrams (Continued)

CDP68HC68T1

CLOCK BUTTON

IGNITION

+

12V

-

5V

REG

LINE

VBATT

POR

XTAL

2MHz

VDD

T1

VSYS

PSE

CPUR

CLK OUT

INT

SPI

VSS

CE

ENABLED POWER

VDD

PORT

RESET

CDP68HC05C4B

OSC1

IRQ

SPI

3

PORT VSS

Example of an automotive system. The VSYS and LINE inputs can be used to sense the ignition turning on and off. An external

switch is included to activate the system without turning on the ignition. Also, the CMOS CPU is not powered down with the system

VDD, but is held in a low power reset mode during power down. When restoring power the CDP68HC68T1 will enable the CLK

OUT pin and set the PSE and CPUR high.

Important Application Note: Those units with a code of 6PG have delayed alarm interrupts of 8.3ms regardless of

CDP68HC68T1’s operating frequency. (See Pin Functions, INT.) In addition, reading the Status Register before delayed alarm acti-

vates will disable alarm signal.

FIGURE 19. AUTOMOTIVE SYSTEM DIAGRAM

20

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