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HSP50215

Digital UpConverter

Intersil 

HSP50215

Functional Description

The HSP50215 Digital UpConverter (DUC) converts digital

baseband data into modulated or frequency translated digital

samples. The DUC can be configured to create any

quadrature amplitude shift-keyed (QASK) data modulated

signal, including QPSK, BPSK, and m-ary QAM. The DUC

can also be configured to create both shaped and unfiltered

FM signals. A minimum of 16 bits of resolution is maintained

throughout the internal processing.

The DUC is configured via the 16-bit microprocessor data

bus, using the address bus and RD, WR and CE control

signals. Configuration data that is loaded via this bus

includes the 30-bit Sample Rate NCO center frequency, the

32-bit Carrier NCO center frequency, the modulation format,

gain control, FIFO control, reset control and sync control.

The I and Q baseband channels each have a 256 tap FIR

filter whose coefficients and configuration are also

programmed via the µP interface. Similarly, the control

signals for the I and Q channel interpolation filters are

programmed via the µP interface. Once the operational

configuration for the device has been set, the 16-bit µP

interface is used to input the I and Q data into the associated

FIFOs.

The FIFOs provide the data interface between the µP and

either the FM modulator or the shaping filters. Multiplexers

route the I data to the FM modulator in the FM with

bandlimiting filter mode. Both I and Q are routed to the 256

tap FIR shaping filters in the QASK mode. The shaping filter

serves to both shape and interpolate the sample rate to 4, 8,

or 16 times the input sample rate. The I shaping filter output

can also be routed to the FM modulator for the FM with pulse

shaping mode. Multiplexers select either the FM modulator

output or the shaping filter output to be scaled and routed to

the interpolation filters.

The I and Q interpolation filters allow a non-integer increase in

sample rate, up to the reference clock rate. The interpolation

filter output data is upconverted or modulated by the Carrier

NCO and multipliers. The modulated signal is added to

modulated inputs from other cascaded DUC’s. The output

formatter sets the output buffer state and the output data

format.

Programmable FIFO

The Programmable FIFOs provide a data storage and

interface between the microprocessor data write holding

register and the shaping filter or the FM modulator. Signal

routing out of the FIFO is set by the modulation format. Each

FIFO has seven 16-bit registers. Figure 1 shows the

conceptual details of the I and Q FIFOs.

A(000)

WR

DFF1

R

E

>G

DFF2

R

E

>G

DFF3

R

E

>G

DFF4

R

E

>G

† ALL REGISTERS

ARE CLOCKED AT

REFCLK UNLESS

SHOWN OTHERWISE

IIN(15:0)

WRITE SHIFT ENABLE

RR

R

R

R

R

R

R

EE

E

E

E

E

E

E

>G >G >G >G >G >G >G

>G

WR

ZERO’S

A(2:0)

8:1 MUX

RTH(2:0)

IFIFO(15:0)

FM ENABLED

QIN(15:0)

8:1 MUX

FIFORDY

QFIFO(15:0)

RR

R

R

R

R

R

R

EE

E

E

E

E

E

E

>G >G >G >G >G >G >G

>G

WR

WRITE SHIFT ENABLE

A(001)

WR

DFF1

R

E

>G

DFF2

R

E

>G

DFF3

R

E

>G

DFF4

R

E

>G

FIGURE 1. I AND Q FIFO BLOCK DIAGRAM

WR

REFCLK

1234

DLY DATA

DFF 1

DFF 2

DFF 3

DFF 4

WR SHFT EN

REG1

FIFO NEEDS

FIFORDY MORE DATA

FIFO NEEDS

MORE DATA

FIGURE 2. FIFORDY AND DATA DELAY TIMING

3-426

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