73K222AU 데이터 시트보기 (PDF) - TDK Corporation
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73K222AU Datasheet PDF : 40 Pages
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73K222AU
Single-Chip Modem
with UART
UART REGISTER BIT DESCRIPTIONS
UART SECTION
RECEIVER BUFFER REGISTER (RBR) (READ ONLY)
STNDLN:
0
1
ADDRESS:
UA2 - UA0 = 000, DLAB = 0
UA3 - UA0 = 0000, DLAB = 0
This read only register contains the parallel received data with start, stop, and parity bits (if any) removed. The
high order bits for less than 8 data bits/character will be set to 0.
TRANSMIT HOLDING REGISTER (THR) (WRITE ONLY)
STNDLN:
0
1
ADDRESS:
UA2 - UA0 = 000, DLAB = 0
UA3 - UA0 = 0000, DLAB = 0
This write only register contains the parallel data to be transmitted. The data is sent LSB first with start, stop, and
parity bits (if any) added to the serial bit stream as the data is transferred.
INTERRUPT ENABLE REGISTER (IER)
STNDLN:
0
ADDRESS:
UA2 - UA0 = 001, DLAB = 0
1
UA3 - UA0 = 0001, DLAB = 0
This 8-bit register enables the four types of interrupts of the UART to separately activate the chip Interrupt
(INTRPT) output signal. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of the
Interrupt Enable Register. Similarly, by setting the appropriate bits of this register to a logic 1, selected interrupts
can be enabled. Disabling the interrupt system inhibits the Interrupt Identification Register and the active (high)
INTRPT output from the chip. All other system functions operate in their normal manner, including the setting of
the Line Status and Modem Status Registers.
BIT NO.
D0
D1
D2
D3
D4
D5 - D7
NAME
Received Data
Transmitter Holding
Register Empty
Receiver Line
Status Interrupt
Modem Status
8250A/16450
Not Used
CONDITION
1
1
1
1
1/0
0
DESCRIPTION
This bit enables the Received Data Available Interrupt
when set to logic 1.
This bit enables the Transmitter Holding Register Empty
Interrupt, when set to logic 1.
This bit enables the Receiver Line Status Interrupt, when
set to logic 1.
This bit enables the Modem Status Register Interrupt
when set to interrupt logic 1.
Set for compatibility with 8250A/16C450 UARTS. Reset
this bit to disable the gating of the INTRPT interrupt line
with the DISTR signal which is needed for 8250B
compatibility.
These three bits are always logic 0.
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