73K222AU 데이터 시트보기 (PDF) - TDK Corporation
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73K222AU Datasheet PDF : 40 Pages
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73K222AU
Single-Chip Modem
with UART
LINE CONTROL REGISTER (LCR)
STNDLN:
0
ADDRESS:
UA2 - UA0 = 011
1
UA3 - UA0 = 0011
UART SECTION
The user specifies the format of the asynchronous data communications exchange via the Line Control Register.
In addition to controlling the format, the user may retrieve the contents of the Line Control Register for inspection.
This feature simplifies system programming and eliminates the need for separate storage in system memory of
the line characteristics.
BIT NO. NAME
D0
Word Length Select 0
D1
Word Length Select 1
D2
Number of Stop Bits
D3
Parity Enable
D4
Even Parity Select
CONDITION
D1
D0
0
0
0
1
1
0
1
1
0 or 1
1
1 or 0
DESCRIPTION
Bits D0 and D1 select the number of data bits per
character as shown:
Word Length
5 bits
6 bits
7 bits
8 bits
This bit specifies the number of stop bits in each
transmitted character. If bit 2 is a logic 0, one stop bit is
generated in the transmitted data. If bit 2 is a logic 1
when a 5-bit word length is selected via bits 0 and 1,
one-and-a-half stop bits are generated. If bit 2 is a logic
1 when either a 6, 7, or 8-bit word length is selected, two
stop bits are generated. The receiver checks the first
stop bit only, regardless of the number of stop bits
selected.
This bit is the Parity Enable bit. When bit 3 is a logic 1, a
parity bit is generated (transmit data) or checked
(receive data) between the last data word bit and stop bit
of the serial data. (The parity bit is used to produce an
even or odd number of 1’s when the data word bits and
the parity bit are summed).
This bit is the Even Parity Select bit. When bit 3 is a
logic 1 and bit 4 is a logic 0, an odd number of logic 1’s
are transmitted or checked in the data word bits and
parity bit. When bit 3 is a logic 1 and bit 4 is a logic 1, an
even number of logic 1’s are transmitted or checked.
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