73K222AU 데이터 시트보기 (PDF) - TDK Corporation

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73K222AU

Single-Chip Modem Modem with UART

TDK Corporation 

73K222AU

Single-Chip Modem

with UART

LINE STATUS REGISTER (LSR)

STNDLN:

0

ADDRESS:

UA2 - UA0 = 101

1

UA3 - UA0 = 0101

This register provides status information to the CPU concerning the data transfer.

UART SECTION

BIT NO.

D0

NAME

DR

D1

OE

D2

PE

D3

FE

D4

BI

D5

THRE

D6

TSRE

D7

-

CONDITION

1

1

1

1

1

1

1

0

DESCRIPTION

The Data Ready (DR) bit is set to a 1 whenever a

complete incoming character has been received and

transferred into the Receiver Buffer Register. Data

Ready is reset to 0 by reading the data in the Receiver

Buffer Register or by writing a 0 into it from the

processor.

The Overrun Error (OE) bit indicates that the data in the

Receiver Buffer Register was not read by the CPU

before the next character was transferred into the

Receiver Buffer Register, thereby destroying the

previous character. The OE indicator is reset whenever

the CPU reads the contents of the Line Status Register.

The Parity Error (PE) bit indicates that the received

character did not have the correct parity. The bit is reset

to 0 whenever the CPU reads the Line Status Register.

The Framing Error (FE) bit indicates that the received

character did not have a valid stop bit. The FE indicator

is reset whenever the CPU reads the contents of the

Line Status Register. A framing error will not occur in

DPSK receive from the modem due to the fact that

missing stop bits are reinserted.

The Break Interrupt (BI) bit indicates that a break has

been received. A break occurs whenever the received

data is held to 0 for a full data word (start + data + stop)

or for two full data words when receiving in DPSK mode

from the modem. The BI bit is reset to 0 whenever the

CPU reads the Line Status Register.

The Transmit Holding Register Empty (THRE) indicates

that the Transmitter is ready to accept a new character

for transmission. The THRE bit is reset when the CPU

loads a character into the Transmit Holding Register.

The Transmit Shift Empty (TSRE) indicates that both the

Transmit Holding Register and the Transmit Shift

Registers are empty.

Always zero.

18

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