PSD834F2-10J 데이터 시트보기 (PDF) - STMicroelectronics

부품명

상세내역

제조사

PSD834F2-10J

Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

STMicroelectronics 

PSD834F2V

Pin Name Pin Type

Description

PC5 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC5) output.

PC5

13

I/O 3. Input to the PLDs.

4. TDI input2 for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PC6 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC6) output.

PC6

12

I/O 3. Input to the PLDs.

4. TDO output2 for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PC7 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

PC7

11

I/O

2. CPLD macrocell (McellBC7) output.

3. Input to the PLDs.

4. DBE – active Low Data Byte Enable input from 68HC912 type MCUs.

This pin can be configured as a CMOS or Open Drain output.

t(s) PD0 pin of Port D. This port pin can be configured to have the following functions:

1. ALE/AS input latches address output from the MCU.

c PD0

10 I/O 2. MCU I/O – write or read from a standard output or input port.

u 3. Input to the PLDs.

d 4. CPLD output (External Chip Select).

ro PD1 pin of Port D. This port pin can be configured to have the following functions:

P 1. MCU I/O – write to or read from a standard output or input port.

te PD1

9

I/O

2. Input to the PLDs.

3. CPLD output (External Chip Select).

le 4. CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter, and

o the CPLD AND Array.

bs PD2 pin of Port D. This port pin can be configured to have the following functions:

O 1. MCU I/O – write to or read from a standard output or input port.

- PD2

8

I/O

2. Input to the PLDs.

3. CPLD output (External Chip Select).

t(s) 4. PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and I/

O. When High, the PSD memory blocks are disabled to conserve power.

c VCC

15, 38

Supply Voltage

rodu GND

1, 16,

26

Ground pins

P Note: 1. The pin numbers in this table are for the PLCC package only. See the package information, on page 90 onwards, for pin numbers

on other package types.

te 2. These functions can be multiplexed with other functions.

bsole PSD REGISTER DESCRIPTION AND ADDRESS OFFSET

OTable 6 shows the offset addresses to the PSD Table 6 provides brief descriptions of the registers

registers relative to the CSIOP base address. The in CSIOP space. The following section gives a

CSIOP space is the 256 bytes of address that is al- more detailed description.

located by the user to the internal PSD registers.

13/95

Share Link: