PSD834F2-10J 데이터 시트보기 (PDF) - STMicroelectronics

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PSD834F2-10J

Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

STMicroelectronics 

PSD834F2V

Reading the Erase/Program Status Bits. The

When the internal cycle is complete, the toggling

PSD provides several status bits to be used by the stops and the data READ on the Data Bus D0-D7

MCU to confirm the completion of an Erase or Pro- is the addressed memory byte. The device is now

gram cycle of Flash memory. These status bits accessible for a new READ or WRITE operation.

minimize the time that the MCU spends perform- The cycle is finished when two successive READs

ing these tasks and are defined in Table 8. The yield the same output data.

status bits can be read as many times as needed. ■ The Toggle Flag (DQ6) Bit is effective after the

For Flash memory, the MCU can perform a READ

fourth WRITE pulse (for a Program instruction)

operation to obtain these status bits while an

or after the sixth WRITE pulse (for an Erase

Erase or Program instruction is being executed by

instruction).

the embedded algorithm. See the section entitled

“Programming Flash Memory”, on page 19, for de-

tails.

■ If the byte to be programmed belongs to a

protected Flash memory sector, the instruction

is ignored.

Data Polling Flag (DQ7). When erasing or pro- ■ If all the Flash memory sectors selected for

gramming in Flash memory, the Data Polling Flag

erasure are protected, the Toggle Flag (DQ6)

(DQ7) Bit outputs the complement of the bit being

Bit toggles to '0' for about 100µs and then

entered for programming/writing on the DQ7 Bit.

returns to the previous addressed byte.

Once the Program instruction or the WRITE oper-

ation is completed, the true logic value is read on

the Data Polling Flag (DQ7) Bit (in a READ opera-

) tion).

t(s ■ Data Polling is effective after the fourth WRITE

c pulse (for a Program instruction) or after the

u sixth WRITE pulse (for an Erase instruction). It

d must be performed at the address being

ro programmed or at an address within the Flash

memory sector being erased.

P ■ During an Erase cycle, the Data Polling Flag

te (DQ7) Bit outputs a '0.' After completion of the

le cycle, the Data Polling Flag (DQ7) Bit outputs

o the last bit programmed (it is a '1' after erasing).

s ■ If the byte to be programmed is in a protected

b Flash memory sector, the instruction is ignored.

O ■ If all the Flash memory sectors to be erased are

- protected, the Data Polling Flag (DQ7) Bit is

) reset to '0' for about 100µs, and then returns to

t(s the previous addressed byte. No erasure is

c performed.

u Toggle Flag (DQ6). The PSD offers another way

d for determining when the Flash memory Program

ro cycle is completed. During the internal WRITE op-

P eration and when either the FS0-FS7 or

CSBOOT0-CSBOOT3 is true, the Toggle Flag

te (DQ6) Bit toggles from '0' to '1' and '1' to '0' on sub-

le sequent attempts to read any byte of the memory.

Error Flag (DQ5). During a normal Program or

Erase cycle, the Error Flag (DQ5) Bit is to '0.' This

bit is set to '1' when there is a failure during Flash

memory Byte Program, Sector Erase, or Bulk

Erase cycle.

In the case of Flash memory programming, the Er-

ror Flag (DQ5) Bit indicates the attempt to program

a Flash memory bit from the programmed state,

'0,' to the erased state, '1,' which is not valid. The

Error Flag (DQ5) Bit may also indicate a Time-out

condition while attempting to program a byte.

In case of an error in a Flash memory Sector Erase

or Byte Program cycle, the Flash memory sector in

which the error occurred or to which the pro-

grammed byte belongs must no longer be used.

Other Flash memory sectors may still be used.

The Error Flag (DQ5) Bit is reset after a Reset

Flash instruction.

Erase Time-out Flag (DQ3). The Erase Time-

out Flag (DQ3) Bit reflects the time-out period al-

lowed between two consecutive Sector Erase in-

structions. The Erase Time-out Flag (DQ3) Bit is

reset to '0' after a Sector Erase cycle for a time pe-

riod of 100µs + 20% unless an additional Sector

Erase instruction is decoded. After this time peri-

od, or when the additional Sector Erase instruction

is decoded, the Erase Time-out Flag (DQ3) Bit is

set to '1.'

o Table 8. Status Bit

ObsFunctional Block

FS0-FS7/CSBOOT0-

CSBOOT3

DQ7

DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

Flash Memory

VIH

Data Toggle Error

Polling Flag Flag

Erase

X Time- X

out

X

X

Note: 1. X = Not guaranteed value, can be read either 1 or 0.

2. DQ7-DQ0 represent the Data Bus Bits, D7-D0.

3. FS0-FS7 and CSBOOT0-CSBOOT3 are active High.

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