PSD834F2-10J 데이터 시트보기 (PDF) - STMicroelectronics

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PSD834F2-10J

Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

STMicroelectronics 

PSD834F2V

Programming Flash Memory

Flash memory must be erased prior to being pro- ming algorithm has completed, to compare the

grammed. A byte of Flash memory is erased to all byte that was written to the Flash memory with the

1s (FFh), and is programmed by setting selected byte that was intended to be written.

bits to '0.' The MCU may erase Flash memory all

at once or by-sector, but not byte-by-byte. Howev-

er, the MCU may program Flash memory byte-by-

byte.

When using the Data Polling method during an

Erase cycle, Figure 4 still applies. However, the

Data Polling Flag (DQ7) Bit is '0' until the Erase cy-

cle is complete. A '1' on the Error Flag (DQ5) Bit in-

The primary and secondary Flash memories re- dicates a time-out condition on the Erase cycle; a

quire the MCU to send an instruction to program a '0' indicates no error. The MCU can read any loca-

byte or to erase sectors (see Table 7).

tion within the sector being erased to get the Data

Once the MCU issues a Flash memory Program or

Erase instruction, it must check for the status bits

Polling Flag (DQ7) Bit and the Error Flag (DQ5)

Bit.

for completion. The embedded algorithms that are PSDsoft Express generates ANSI C code func-

invoked inside the PSD support several means to tions which implement these Data Polling algo-

provide status to the MCU. Status may be checked rithms.

using any of three methods: Data Polling, Data

Toggle, or Ready/Busy (PC3).

Figure 4. Data Polling Flowchart

Data Polling. Polling on the Data Polling Flag

) (DQ7) Bit is a method of checking whether a Pro-

t(s gram or Erase cycle is in progress or has complet-

ed. Figure 4 shows the Data Polling algorithm.

c When the MCU issues a Program instruction, the

u embedded algorithm within the PSD begins. The

rod MCU then reads the location of the byte to be pro-

grammed in Flash memory to check status. The

P Data Polling Flag (DQ7) Bit of this location be-

te comes the complement of b7 of the original data

byte to be programmed. The MCU continues to

le poll this location, comparing the Data Polling Flag

o (DQ7) Bit and monitoring the Error Flag (DQ5) Bit.

s When the Data Polling Flag (DQ7) Bit matches b7

b of the original data, and the Error Flag (DQ5) Bit

O remains '0,' the embedded algorithm is complete.

- If the Error Flag (DQ5) Bit is '1,' the MCU should

) test the Data Polling Flag (DQ7) Bit again since

t(s the Data Polling Flag (DQ7) Bit may have changed

simultaneously with the Error Flag (DQ5) Bit (see

c Figure 4).

du The Error Flag (DQ5) Bit is set if either an internal

ro time-out occurred while the embedded algorithm

attempted to program the byte or if the MCU at-

P tempted to program a '1' to a bit that was not

te erased (not erased is logic 0).

le It is suggested (as with all Flash memories) to read

Obso the location again after the embedded program-

START

READ DQ5 & DQ7

at VALID ADDRESS

DQ7

=

YES

DATA

NO

NO DQ5

=1

YES

READ DQ7

DQ7

=

YES

DATA

NO

FAIL

PASS

AI01369B

19/95

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