MSP34X5G 데이터 시트보기 (PDF) - Unspecified

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MSP34X5G

Multistandard Sound Processor Family

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PRELIMINARY DATA SHEET

MSP 34x5G

3. Control Interface

3.1. I2C Bus Interface

The MSP 34x5G is controlled via the I2C bus slave

interface.

The IC is selected by transmitting one of the

MSP 34x5G device addresses. In order to allow up to

three MSP ICs to be connected to a single bus, an

address select pin (ADR_SEL) has been implemented.

With ADR_SEL pulled to high, low, or left open, the

MSP 34x5G responds to different device addresses. A

device address pair is defined as a write address and a

read address (see Table 3–1).

Writing is done by sending the write device address,

followed by the subaddress byte, two address bytes,

and two data bytes.

Reading is done by sending the write device address,

followed by the subaddress byte and two address

bytes. Without sending a stop condition, reading of the

addressed data is completed by sending the device

read address and reading two bytes of data.

Refer to Section 3.1.3. for the I2C bus protocol and to

Section 3.4. “Programming Tips” on page 37 for pro-

posals of MSP 34x5G I2C telegrams. See Table 3–2

for a list of available subaddresses.

Besides the possibility of hardware reset, the MSP can

also be reset by means of the RESET bit in the CON-

TROL register by the controller via I2C bus.

Due to the architecture of the MSP 34x5G, the IC can-

not react immediately to an I2C request. The typical

Table 3–1: I2C Bus Device Addresses

response time is about 0.3 ms. If the MSP cannot

accept another byte of data (e.g. while servicing an

internal interrupt), it holds the clock line I2C_CL low to

force the transmitter into a wait state. The I2C Bus

Master must read back the clock line to detect when

the MSP is ready to receive the next I2C transmission.

The positions within a transmission where this may

happen are indicated by ’Wait’ in Section 3.1.3. The

maximum wait period of the MSP during normal opera-

tion mode is less than 1 ms.

3.1.1. Internal Hardware Error Handling

In case of any hardware problems (e.g. interruption of

the power supply of the MSP), the MSP’s wait period is

extended to 1.8 ms. After this time period elapses, the

MSP releases data and clock lines.

Indication and solving the error status:

To indicate the error status, the remaining acknowl-

edge bits of the actual I2C-protocol will be left high.

Additionally, bit[14] of CONTROL is set to one. The

MSP can then be reset via the I2C bus by transmitting

the RESET condition to CONTROL.

Indication of reset:

Any reset, even caused by an unstable reset line etc.,

is indicated in bit[15] of CONTROL.

A general timing diagram of the I2C bus is shown in

Fig. 4–27 on page 61.

ADR_SEL

Mode

MSP device address

Low

(connected to DVSS)

Write

Read

80hex

81hex

High

(connected to DVSUP)

Write

Read

84hex

85hex

Left Open

Write

88hex

Read

89hex

Table 3–2: I2C Bus Subaddresses

Name

CONTROL

Binary Value

0000 0000

Hex Value

00

WR_DEM

0001 0000

10

RD_DEM

0001 0001

11

WR_DSP

0001 0010

12

RD_DSP

0001 0011

13

Mode

Read/Write

Write

Write

Write

Write

Function

Write: Software reset of MSP (see Table 3–3)

Read: Hardware error status of MSP

write address demodulator

read address demodulator

write address DSP

read address DSP

Micronas

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