MSP34X5G 데이터 시트보기 (PDF) - Unspecified

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MSP34X5G

Multistandard Sound Processor Family

Unspecified 

MSP 34x5G

PRELIMINARY DATA SHEET

3.1.2. Description of CONTROL Register

Table 3–3: CONTROL as a Write Register

Name

Subaddress

CONTROL 00hex

Bit[15] (MSB)

1 : RESET

0 : normal

Bits[14:0]

0

Table 3–4: CONTROL as a Read Register

Name

Subaddress %LW>@ 06%

Bit>@

BitV>@

CONTROL 00hex

RESET status after last reading of

CONTROL:

0 : no reset occured

1 : reset occured

Internal hardware status:

0 : no error occured

1 : internal error occured

not of interest

Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on, bit[15] of CONTROL will be set; it must be

read once to be reset.

3.1.3. Protocol Description

Write to DSP or Demodulator

S write Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK data-byte ACK data-byte ACK P

device

high

low

high

low

address

Read from DSP or Demodulator

S write Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK S read Wait ACK data-byte- ACK data-byte NAK P

device

high

low

device

high

low

address

address

Write to Control Register

S write Wait ACK sub-addr ACK data-byte ACK data-byte ACK P

device

high

low

address

Read from Control Register

S write Wait ACK

device

address

00hex

ACK S read Wait ACK data-byte- ACK data-byte NAK P

device

high

low

address

Note: S = I2C-Bus Start Condition from master

P = I2C-Bus Stop Condition from master

ACK = Acknowledge-Bit: LOW on I2C_DA from slave (= MSP, light gray) or master (= controller, dark gray)

NAK = Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate ‘End of Read’

or from MSP indicating internal error state

Wait = I2C-Clock line is held low, while the MSP is processing the I2C command.

This waiting time is max. 1 ms

16

Micronas

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