FP101 데이터 시트보기 (PDF) - WJ Communications => Triquint

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FP101

High Dynamic Range FET

WJ Communications => Triquint 

FP101

High Dynamic Range FET

Outline Drawing

The Communications Edge TM

Product Information

Product Marking

The component will be marked with an “FP101”

designator with a four- or five-digit alphanumeric lot

code on the top surface of the package. Tape and reel

specifications for this part is located on the website in

the “Application Notes” section.

Land Pattern

ESD / MSL Information

ESD Classification:

Value:

Test:

Standard:

Class 1C

Passes !1000 V to <2000 V

Human Body Model (HBM)

JEDEC Standard JESD22-A114

ESD Classification:

Value:

Test:

Standard:

Class IV

Passes !1000 V

Charged Device Model (CDM)

JEDEC Standard JESD22-C101

MSL Rating:

Standard:

Level 3 at +235 °C convection reflow

JEDEC Standard J-STD-020A

Mounting Config. Notes

1. Ground / thermal vias are critical for the proper

performance of this device. Vias should use a .35mm

(#80 / .0135”) diameter drill and have a final plated thru

diameter of .25 mm (.010”).

2. Add as much copper as possible to inner and outer

layers near the part to ensure optimal thermal

performance.

3. Mounting screws can be added near the part to fasten

the board to a heatsink. Ensure that the ground /

thermal via region contacts the heatsink.

4. Do not put solder mask on the backside of the PC board

in the region where the board contacts the heatsink.

5. RF trace width depends upon the PC board material and

construction.

6. Use 1 oz. Copper minimum.

7. All dimensions are in millimeters (inches). Angles are

in degrees.

Specifications and information are subject to change without notice.

WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: sales@wj.com • Web site: www.wj.com

September 2003

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