NT6828 데이터 시트보기 (PDF) - Novatek Microelectronics

부품명

상세내역

제조사

NT6828

I2C Bus Controlled On-Screen Display

Novatek Microelectronics 

NT6828

(7) Flexible Display Control Register: Row 15, Column 15

Row 15

Column 15

7

6

54

3

2

1

HDR

MSB

Horizontal Display Resolution Control

0

LSB

Bit 6 - 0: HDR- These bits determine the resolution of horizontal display line. The unit of this setting is 12 dots

(1 character). With a total of 92, the user can adjust the resolution from 36 to 127 characters on each horizontal

line steps ($24 - $7F: 36 - 127 steps; note that its value can not be smaller than 36 at any given time.) Also

make a special note that the resolution adjustment must be joined together with the VCO setting at row15 /

column18 control register. The default value is 40 after power-on.

(Please refer to the Table showing the control register at row15 / column18.)

(8) OSD Row to Row Space Control Register: Row 15, Column 16

Row 15

Column 16

7

6

5

4

3

2

1

0

R2RSPACE

MSB

LSB

Row To Row Space Adjustment

Bit 4 - 0: R2RSPACE- These bits define the row to row spacing in unit of horizontal line. It means extra lines, defined by

this 5-bit value, will be appended for each display row. The default value of it is 0 after power-on and there is no

any extra line inserted between each row.

(9) Input/Output Control Register: Row 15, Column 17

Row 15

Column 17

7

6

OSDEN BSEN

5

4

3

2

1

0

SHADOW RGBF BLANK CLRWIN CLRDSPR FBKGC

OSD Screen Control 1

Bit 7: OSDEN- This bit will enable the OSD circuit as it is set to ‘1’. The default value is ‘0’ after power-on.

Bit 6: BSEN- This bit will enable the bordering and shadowing effect as it is set to ‘1’. The default value of this bit is ‘0’

after power-on.

Bit 5: SHADOW- When the BSEN is set to ‘1’, it will enable the shadowing effect as this bit set to ‘1’. Otherwise, it will

enable the bordering effect as this bit cleared to ‘0’. The default value is ‘0’ after power-on. (Please refer to Figure

6)

Bit 4: RGBF- This bit controls the driving state of the output pins, R, G, B and FBKG when the OSD is disabled. After

power-on, this bit is cleared to ‘0’ and all of the R, G, B and FBKG pins output at high impedance state while the

OSD being disabled. If this bit is set to ‘1’, these R, G, B pins will drive low while OSD is being disabled, but the

FBKG pins will output ‘0’ if the FBKGP bit is set to ‘1’, whereas output ‘1’, set to ‘0’.

Bit 3: BLANK- This bit will force the FBKG pin to output high as it is set to ‘1’. The default value of this bit is ‘0’ after

power-on.

Bit 2: CLRWIN- This bit will clear all of windows’ WINEN control bit as it is set to ‘1’. The default value of this bit is ‘0’

after power-on.

Bit 1: CLRDSPR- This bit will clear all of the contents in the display registers as it is set to ‘1’. The default value of this bit

is ‘0’ after power-on.

Bit 0: FBKGC This bit determines the configuration of FBKG output pin. When it is cleared, the FBKG pin will output high

while displaying characters or windows. Otherwise, it will output high only while displaying characters. The default

value is ‘0’ after power-on. Please refer to Figure 7 for the FBKG O/P timing.

15

Share Link: