NT6828 데이터 시트보기 (PDF) - Novatek Microelectronics
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NT6828 Datasheet PDF : 31 Pages
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NT6828
(11) PWM Channels Control Registers: Row 15, Column 19 - 26
7
6
Row 15
Column 19-26
MSB
5
4
3
2
PWM Channel Control
1
0
LSB
Bit 7 - 0: These bits determine the output duty cycle and waveforms of PWM. When these bits are set to 00H, the DAC
will output LOW (GND level). After power-on, all of PWM will output low ($00).
Table 7. PWM Clock & Pixel Clock Relationship
Section VCO1 VCO0 VCO Freq. Min VCO Freq. Max Unit PWM CLK PWM Refresh Rate
Freq1
0
0
6
12
Freq1
Freq1 / 256
Freq2
0
1
12
Freq3
1
0
24
24
Freq2/2
Freq2 / 2 / 256
MHz
48
Freq3/4
Freq3 / 4 / 256
Freq4
1
1
48
92.2
Freq4 /8
Freq4 / 8 / 256
Note: Each of PWM channel will be separated by half of PWM clock. (Each has an 8-bit resolution.)
PWMCLK
0123
M-1 M M+1
PWM0
PWM1
...
PWM6
PWM7
255 0 1 2 3
Figure 8. PWMCLK and PWM O/P timing
18
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