NT6828 데이터 시트보기 (PDF) - Novatek Microelectronics

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NT6828

I2C Bus Controlled On-Screen Display

Novatek Microelectronics 

NT6828

3. I2C Bus Communication:

The relative figure shows the I2C Bus transmission format. The master initiates a transmission routine by generating a

START condition, followed by a slave address byte. Once the address is properly identified, the slave will respond with an

ACKNOWLEDGE signal by pulling the SDA line LOW during the ninth SCL clock. Each data byte which then follows must be

eight bits long, plus the ACKNOWLEDGE bit, which makes up nine bits all together. Appropriate row and column address

information and display data can be downloaded sequentially in one of the three transmission formats described in Figure

“Access Register Operation”. In the cases of no ACKNOWLEDGE or completion of data transfer, the master will generate a

STOP condition to terminate the transmission routine. Note that the OSD_EN bit must be set after all the display information

has been sent in order to activate the displaying circuitry of NT6828, so that the received information can then be displayed.

(1) Access the Display Control Registers:

After proper identification by the receiving device, the data train of arbitrary length is transmitted from the master. There are

three transmission formats from (a) to (c) as referred to Figure 9 & Table 8. The data train in each sequence consists of row

addresses, column addresses, and data. In format (a), data must be preceded with the corresponding row address and

column address. This format is particularly suitable for updating small amounts of data between different rows. However, if

the current information byte has the same row address as the one before, format (b) is recommended. For a full screen

pattern change (which requires a massive information update), or during a power-on situation, most of the row and column

addresses on either (a) or (b) format will appear to be redundant. A more efficient data transmission format (c) should be

applied. This sends the starting row and column addresses once only, and then treats all subsequent data as display

information. The row and column addresses will be automatically incremented internally for each display information data

from the starting location.

To differentiate the row and column addresses when transferring data from master, the MSB (Most Significant Bit) is set as

in Table Transmission: ‘1’ represents row, while ‘0’ represents column address. Furthermore, to distinguish the column

address between format (a), (b) and (c); the sixth bit of the column address is set to ‘1’, which represents format (c), and a ‘0’

for format (a) or (b). There is some limitation when using mix-formats during a single transmission. It is permissible to change

the format from (a) to (b), or from (a) to (c), or from (b) to (a), but not from (c) back to (a) or (b).

(2) Access the RAM Fonts Area:

There are some differences when accessing the RAM font. One font consists of 18 rows and 12 columns of dot matrix. At

each row of one font, there are 18 bits of data which allocates 2 bytes of control data with 4 unavailable bits. Thus, each font

occupies 36 bytes of control data. From the memory map of RAM fonts, font0 is allocated at row 0 & column 0 - 35, and

font1, row 1 & column 0 ~ 35, etc. (Please refer to Figure 9.)

Table 8. Address Data Transmission for Registers

ITEM

No

1

Display Register

2

3

4

Attribute / Control

Register

5

6

7

RAM Fonts

8

9

ADDRESS

Row

Column

Column

Row

Column

Column

Row

Column

Column

B7 B6 B5 B4 B3 B2 B1 B0

1 0 0 XDDDD

0 0 XDDDDD

0 1 XDDDDD

1 0 1 XDDDD

0 0 XDDDDD

0 1 XDDDDD

1 1XXXDDD

0 0DDDDDD

0 1DDDDDD

Type

(a), (b), (c)

(a), (b)

(c)

(a), (b), (c)

(a), (b)

(c)

(a), (b), (c)

(a), (b)

(c)

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