LF3310QC15 데이터 시트보기 (PDF) - LOGIC Devices Incorporated
부품명
상세내역
제조사
LF3310QC15 Datasheet PDF : 21 Pages
| |||
DEVICES INCORPORATED
LF3310
Horizontal / Vertical Digital Image Filter
TABLE 8. HCF/VCF11-9 DECODE
11 10 9 DESCRIPTION
0 0 0 Coefficient Banks
0 0 1 Configuration Registers
0 1 0 Horizontal Select Registers
0 1 1 Vertical Select Registers
1 0 0 Horizontal Round Registers
1 0 1 Vertical Round Registers
1 1 0 Horizontal Limit Registers
1 1 1 Vertical Limit Registers
Vertical Rounding
The vertical filter output may be
rounded by adding the contents of
one of the sixteen vertical round
registers to the vertical filter output
(see Figure 11). Each round register is
32-bits wide and user-programmable.
This allows the filter’s output to be
rounded to any precision required.
Since any 32-bit value may be
programmed into the round registers,
the device can support complex
rounding algorithms as well as
standard Half-LSB rounding.
VRSL3-0 determines which of the
sixteen vertical round registers are
used in the rounding operation. A
value of 0 on VRSL3-0 selects vertical
round register 0. A value of 1 selects
vertical round register 1 and so on.
VRSL3-0 may be changed every clock
cycle if desired. This allows the
rounding algorithm to be changed
every clock cycle. This is useful when
filtering interleaved data. If rounding
is not desired, a round register should
be loaded with 0 and selected as the
register used for rounding. Round
register loading is discussed in the LF
InterfaceTM section.
Vertical Select
The word width of the vertical filter
output is 32-bits. However, only
12-bits may be sent to the filter
output. The vertical filter select
circuitry determines which 12-bits are
passed (see Table 1). The vertical
select registers control the vertical
select circuitry. There are sixteen
vertical select registers. Each select
TABLE 9. HRZ. ROUND REGISTERS
REGISTER
ADDRESS (HEX)
0
800
1
801
14
80E
15
80F
TABLE 10. HRZ. SELECT REGISTERS
REGISTER
ADDRESS (HEX)
0
400
1
401
14
40E
15
40F
TABLE 11. HRZ. LIMIT REGISTERS
REGISTER
ADDRESS (HEX)
0
C00
1
C01
14
C0E
15
C0F
register is 5-bits wide and
user-programmable. VRSL3-0 deter-
mines which of the sixteen vertical
select registers are used in the vertical
select circuitry. A value of 0 on
VRSL3-0 selects vertical select register
0. A value of 1 selects vertical select
register 1 and so on. VRSL3-0 may be
changed every clock cycle if desired.
This allows the 12-bit window to be
changed every clock cycle. This is
useful when filtering interleaved
data. Select register loading is
discussed in the LF InterfaceTM
section.
Vertical Limiting
An output limiting function is pro-
vided for the output of the vertical
filter. The vertical limit registers
determine the valid range of output
values when limiting is enabled (Bit 0
in Configuration Register 5). There
TABLE 12. VRT. ROUND REGISTERS
REGISTER
ADDRESS (HEX)
0
A00
1
A01
14
A0E
15
A0F
TABLE 13. VRT. SELECT REGISTERS
REGISTER
ADDRESS (HEX)
0
600
1
601
14
60E
15
60F
TABLE 14. VRT. LIMIT REGISTERS
REGISTER
ADDRESS (HEX)
0
E00
1
E01
14
E0E
15
E0F
are sixteen 24-bit vertical limit
registers. VRSL3-0 determines which
vertical limit register is used during
the limit operation. A value of 0 on
VRSL3-0 selects vertical limit register
0. A value of 1 selects vertical limit
register 1 and so on. Each limit
register contains both an upper and
lower limit value. If the value fed to
the limiting circuitry is less than the
lower limit, the lower limit value is
passed as the filter output. If the
value fed to the limiting circuitry is
greater than the upper limit, the upper
limit value is passed as the filter output.
VRSL3-0 may be changed every clock
cycle if desired. This allows the limit
range to be changed every clock cycle.
This is useful when filtering interleaved
data. When loading limit values into
the device, the upper limit must be
greater than the lower limit. Limit
register loading is discussed in the LF
InterfaceTM section.
Video Imaging Products
11
11/08/2001-LDS.3310-H
Share Link: 