SI3011-F-GS 데이터 시트보기 (PDF) - Silicon Laboratories

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SI3011-F-GS

PROGRAMMABLE VOICE DAA SOLUTIONS

Silicon Laboratories 

Si3050 + Si3011/18/19

Table 7. Switching Characteristics—Serial Peripheral Interface

(VIO = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF)

Parameter*

Cycle Time SCLK

Rise Time, SCLK

Fall Time, SCLK

Delay Time, SCLK Fall to SDO Active

Delay Time, SCLK Fall to SDO

Transition

Delay Time, CS Rise to SDO Tri-state

Setup Time, CS to SCLK Fall

Hold Time, SCLK to CS Rise

Setup Time, SDI to SCLK Rise

Hold Time, SCLK Rise to SDI Transition

Delay time between chip selects

Propagation Delay, SDI to SDITHRU

Symbol

Test

Conditions

Min

Typ

tc

61.03

—

tr

—

—

tf

—

—

td1

—

—

td2

—

—

td3

—

—

tsu1

25

—

th1

20

—

tsu2

25

—

th2

20

—

tcs

220

—

—

6

Max

—

25

25

20

20

20

—

—

—

—

—

—

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

*Note: All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are

VIH = VD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.

SCLK

CS

SDI

SDO

tr

tsu1

td1

tc

tsu2

th2

td2

tf

th1

tcs

td3

Figure 3. SPI Timing Diagram

Rev. 1.5

11

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