A80486DX4WB100SK101 데이터 시트보기 (PDF) - Intel
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A80486DX4WB100SK101 Datasheet PDF : 49 Pages
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EMBEDDED WRITE-BACK ENHANCED
IntelDX4™ PROCESSOR
s Up to 100 MHz Operation
s Integrated Floating-Point Unit
s Speed-Multiplying Technology
s 32-Bit RISC Technology Core
s 16-Kbyte Write-Back Cache
s 3.3 V Core Operation with 5 V Tolerant
I/O Buffers
s Burst Bus Cycles
s Dynamic Bus Sizing for 8- and 16-bit
Data Bus Devices
s SL Technology
s Data Bus Parity Generation and Checking
s Boundary Scan (JTAG)
s 3.3-Volt Processor, 75 MHz, 25 MHz CLK
— 208-Lead Shrink Quad Flat Pack (SQFP)
s 3.3-Volt Processor, 100 MHz, 33 MHz CLK
— 208-Lead Shrink Quad Flat Pack (SQFP)
— 168-Pin Pin Grid Array (PGA)
s Binary Compatible with Large Software
Base
64-Bit Interunit Transfer Bus
32-Bit Data Bus
32-Bit Data Bus
Linear Address
32
Barrel
Shifter
Register
File
Base/
Index
Bus
32
ALU
Segmentation
Unit
Descriptor
Registers
Limit and
Attribute PLA
Paging
Unit
PCD
PWT
2
20
Cache Unit
Translation
Lookaside
Buffer
Physical
Address
16 Kbyte
Cache
Micro-
Instruction
Displacement Bus
32
Prefetcher
Floating
Point Unit
Control &
Protection
Test Unit
Instruction
Decode
Code
Stream
24
32-Byte Code
Queue
2 x 16 Bytes
Floating
Point
Register File
Control
ROM
Decoded
Instruction
Path
Core
Clock
Clock
Multiplier
CLKMUL
CLK
Bus Interface
32
Address
Drivers
A31-A2 BE3#- BE0#
Write Buffers
32
4 x 32
D31-D0
Data Bus
32
Transceivers
Bus Control
Request
Sequencer
ADS# W/R# D/C# M/IO# PCD
PWT RDY# LOCK# PLOCK#
BOFF# A20M# BREQ HOLD
HLDA RESET SRESET INTR
NMI SMI# SMIACT# FERR#
IGNNE# STPCLK#
Burst Bus
Control
Bus Size
Control
Cache
Control
BRDY# BLAST#
BS16# BS8#
KEN# FLUSH# AHOLD EADS#
CACHE# HITM# INV WB/WT#
Parity
Generation
and Control
Boundary
Scan
Control
PCHK# DP3-DP0
TCK TMS TDI TDO
A3232-01
Figure 1. Embedded Write-Back Enhanced IntelDX4™ Processor Block Diagram
© INTEL CORPORATION, 2004
August 2004
Order Number: 272771-003
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