A80486DX4WB100SK101 데이터 시트보기 (PDF) - Intel

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A80486DX4WB100SK101

EMBEDDED WRITE-BACK ENHANCED IntelDX4™ PROCESSOR

Intel 

Embedded Write-Back Enhanced IntelDX4™ Processor

1.0 INTRODUCTION

The embedded Write-Back Enhanced IntelDX4™

processor provides high performance to 32-bit,

embedded applications. Designed for applications

that need a floating-point unit, the processor is ideal

for embedded designs running DOS*, Microsoft

Windows*, OS/2*, or UNIX* applications written for

the Intel architecture. Projects can be completed

quickly using the wide range of software tools,

utilities, assemblers and compilers that are available

for desktop computer systems. Also, developers can

find advantages in using existing chipsets and

peripheral components in their embedded designs.

The Embedded Write-Back Enhanced IntelDX4

processor is binary compatible with the Intel386™

and earlier Intel processors. Compared with the

Intel386 processor, it provides faster execution of

many commonly-used instructions. It also provides

the benefits of an integrated, 16-Kbyte, write-back

cache for code and data. Its data bus can operate in

burst mode which provides up to 106-Mbyte-per-

second transfers for cache-line fills and instruction

prefetches.

Intel’s SL technology is incorporated in the

Embedded Write-Back Enhanced IntelDX4

processor. Utilizing Intel’s System Management

Mode (SMM) enables designers to develop energy-

efficient systems.

Two component packages are available:

• 168-pin Pin Grid Array (PGA)

• 208-lead Shrink Quad Flat Pack (SQFP)

The processor operates at either two or three times

the external bus frequency. At two times the external

bus frequency the processor operates up to 66 MHz,

(33-MHz CLK). At three times the external bus

frequency the processor operates up to 100 MHz

(33-MHz CLK).

1.1 Features

The Embedded Write-Back Enhanced IntelDX4

processor offers these features:

• 32-bit RISC-Technology Core — The Embedded

Write-Back Enhanced IntelDX4 processor

performs a complete set of arithmetic and logical

operations on 8-, 16-, and 32-bit data types using

a full-width ALU and eight general purpose

registers.

• Single Cycle Execution — Many instructions

execute in a single clock cycle.

• Instruction Pipelining — Overlapped instruction

fetching, decoding, address translation and

execution.

• On-Chip Floating-Point Unit — Intel486™

processors support the 32-, 64-, and 80-bit formats

specified in IEEE standard 754. The unit is binary

compatible with the 8087, Intel287™, Intel387™

coprocessors, and Intel OverDrive® processor.

• On-Chip Cache with Cache Consistency

Support — A 16-Kbyte internal cache is used for

both data and instructions. It is configurable to be

write-back or write-through on a line-by-line basis.

The internal cache implements a modified MESI

protocol, which is applicable to uniprocessor

systems. Cache hits provide zero wait-state

access times for data within the cache. Bus activity

is tracked to detect alterations in the memory

represented by the internal cache. The internal

cache can be invalidated or flushed so that an

external cache controller can maintain cache

consistency.

• External Cache Control — Write-back and flush

controls for an external cache are provided so the

processor can maintain cache consistency.

• On-Chip Memory Management Unit — Address

management and memory space protection

mechanisms maintain the integrity of memory in a

multitasking and virtual memory environment. Both

memory segmentation and paging are supported.

• Burst Cycles — Burst transfers allow a new

double-word to be read from memory on each bus

clock cycle. This capability is especially useful for

instruction prefetch and for filling the internal

cache. Data written from the processor to memory

can also be burst transfers.

• Write Buffers — The processor contains four

write buffers to enhance the performance of

consecutive writes to memory. The processor can

continue internal operations after a write to these

buffers, without waiting for the write to be

completed on the external bus.

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