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TTSI1K16T3TL

1024-Channel, 16-Highway Time-Slot Interchanger

Agere -> LSI Corporation 

Preliminary Data Sheet

February 1999

TTSI1K16T

1024-Channel, 16-Highway Time-Slot Interchanger

Pin Information (continued)

Table 4. TTSI1K16T Pin Descriptions (continued)

Symbol

Type*

Description

D[7—0]

I/O Host Processor Data Bus. These pins Host Processor Data Bus. These pins

provide an 8-bit, bidirectional data bus. provide an 8-bit, bidirectional data bus.

Read data is valid for one PCLK cycle Write data must be valid for the duration

coincident with the assertion of DT. Write of DS. Read data is valid while DT is

data must be held throughout the

asserted.

access.

A[14—0]

I Host Processor Address Bus. A14—A0 must remain valid throughout the entire

processor access. A0 is the least significant address signal and is used to select

byte locations.

R/W

I Read/Write. This signal indicates a read or write cycle. Read cycle is indicated with

a logic 1; a write cycle is indicated with a logic 0.

INT

O Interrupt. This pin will be asserted to indicate that an interrupt condition has

occurred. This output will remain active until the interrupt status register has been

cleared (read). The polarity of this output is controlled through the INTP bit (bit 3) of

the general command register. The default value of this register is 0, which indi-

cates active-high. This output is tristated until INTOE (bit 4) of the general command

register is set to 1. The polarity of this output should be selected before the pin is

enabled.

RXD[0—15]

Iu Receive Data Highways 0—15. Serial TDM highways receiving data at rates of

2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s.

FSYNC

I Frame Synchronization. This signal indicates the beginning of a frame every

125 µs (8 kHz). FSYNC can be active-low or active-high, but its polarity is the same

for all highways. FSYNC can be sampled on a positive or negative CK edge. Time-

slot numbers and bit offsets are assigned relative to the detection of FSYNC. There

are no restrictions on the duty cycle of FSYNC as long as the setup and hold timing

requirements relative to CK are met.

CK

I Clock. This input is the clock reference for all the transmit and receive highways. Its

frequency can be 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz. The fre-

quency selection for CK must be set equal to or greater than the fastest highway

data rate.

CKSPD[2—0]

I Clock Speed Select for CK Pin. These strap pins indicate the frequency of CK:

CKSPD2

0

0

0

0

1

CKSPD1

0

0

1

1

X

CKSPD0

0

1

0

1

X

CK (MHz)

2.048

4.096

8.192

16.384

Reserved

TXD[0—15]

O Transmit Data Highways 0—15. Serial TDM highway transmitting data at rates of

2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s. During external driver mode, the

TXD[0—15] outputs will be continuously driven. The only exception to this is when

the TEST input is asserted. When not in external driver mode, this highway can be

tristated on a per-time-slot basis.

See Table 41, Transmit Highway 3-State Options, on page 49 for a detailed descrip-

tion of all methods for 3-stating the transmit highways.

*Iu indicates internal 100 kΩ pull-up resistor, and Id indicates 17.5 kΩ pull-down resistor.

Lucent Technologies Inc.

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