LFE3-70EA-7LFTN256I 데이터 시트보기 (PDF) - Lattice Semiconductor

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LFE3-70EA-7LFTN256I

LatticeECP3 Family Data Sheet Introduction

Lattice Semiconductor 

Architecture

LatticeECP3 Family Data Sheet

PLL/DLL Cascading

LatticeECP3 devices have been designed to allow certain combinations of PLL and DLL cascading. The allowable

combinations are:

• PLL to PLL supported

• PLL to DLL supported

The DLLs in the LatticeECP3 are used to shift the clock in relation to the data for source synchronous inputs. PLLs

are used for frequency synthesis and clock generation for source synchronous interfaces. Cascading PLL and DLL

blocks allows applications to utilize the unique benefits of both DLLs and PLLs.

For further information about the DLL, please see the list of technical documentation at the end of this data sheet.

PLL/DLL PIO Input Pin Connections

All LatticeECP3 devices contains two DLLs and up to ten PLLs, arranged in quadrants. If a PLL and a DLL are next

to each other, they share input pins as shown in the Figure 2-7.

Figure 2-7. Sharing of PIO Pins by PLLs and DLLs in LatticeECP3 Devices

PLL_PIO

PLL

DLL_PIO

DLL

Note: Not every PLL has an associated DLL.

Clock Dividers

LatticeECP3 devices have two clock dividers, one on the left side and one on the right side of the device. These are

intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2, ÷4 or

÷8 mode and maintains a known phase relationship between the divided down clock and the high-speed clock

based on the release of its reset signal. The clock dividers can be fed from selected PLL/DLL outputs, the Slave

Delay lines, routing or from an external clock input. The clock divider outputs serve as primary clock sources and

feed into the clock distribution network. The Reset (RST) control signal resets input and asynchronously forces all

outputs to low. The RELEASE signal releases outputs synchronously to the input clock. For further information on

clock dividers, please see TN1178, LatticeECP3 sysCLOCK PLL/DLL Design and Usage Guide. Figure 2-8 shows

the clock divider connections.

2-10

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