LFE3-70EA-7LFTN256I 데이터 시트보기 (PDF) - Lattice Semiconductor

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LFE3-70EA-7LFTN256I

LatticeECP3 Family Data Sheet Introduction

Lattice Semiconductor 

Architecture

LatticeECP3 Family Data Sheet

Figure 2-10. Primary Clock Sources for LatticeECP3-35

Clock Input Clock Input

From Routing

PLL Input

PLL

PLL

PLL Input

Clock

Input

Clock

Input

DLL Input

Primary Clock Sources

to Eight Quadrant Clock Selection

CLK

CLK

DIV

DIV

DLL

DLL

Clock

Input

Clock

Input

DLL Input

PLL Input

PLL

PLL

SERDES

Quad

From Routing

Note: Clock inputs can be configured in differential or single-ended mode.

Figure 2-11. Primary Clock Sources for LatticeECP3-70, -95, -150

Clock Input Clock Input

From Routing

PLL Input

PLL

PLL

PLL Input

Clock

Input

Clock

Input

DLL Input

PLL

PLL

Primary Clock Sources

to Eight Quadrant Clock Selection

CLK

CLK

DIV

DIV

DLL

DLL

PLL Input

PLL Input

PLL Input

Clock

Input

Clock

Input

DLL Input

PLL Input

PLL Input

PLL Input

PLL

PLL

PLL

PLL

PLL

SERDES

Quad

SERDES

Quad

SERDES

Quad

SERDES

Quad

(ECP3-150 only)

PLL

From Routing

Note: Clock inputs can be configured in differential or single-ended mode.

2-12

PLL Input

PLL Input

PLL Input

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