LFE3-70EA-7LFTN256I 데이터 시트보기 (PDF) - Lattice Semiconductor

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LFE3-70EA-7LFTN256I

LatticeECP3 Family Data Sheet Introduction

Lattice Semiconductor 

Architecture

LatticeECP3 Family Data Sheet

Table 2-6. Secondary Clock Regions

Device

ECP3-17

ECP3-35

ECP3-70

ECP3-95

ECP3-150

Number of Secondary Clock

Regions

16

16

20

20

36

Figure 2-15. LatticeECP3-70 and LatticeECP3-95 Secondary Clock Regions

Vertical Routing Channel

Regional Boundary

sysIO Bank 0

sysIO Bank 1

Secondary Clock Secondary Clock Secondary Clock Secondary Clock

Region R1C1

Region R1C2

Region R1C3

Region R1C4

EBR Row

Regional Boundary

Secondary Clock Secondary Clock Secondary Clock Secondary Clock

Region R2C1

Region R2C2

Region R2C3

Region R2C4

Secondary Clock Secondary Clock Secondary Clock Secondary Clock

Region R3C1

Region R3C2

Region R3C3

Region R3C4

Secondary Clock Secondary Clock Secondary Clock Secondary Clock

Region R4C1

Region R4C2

Region R4C3

Region R4C4

Secondary Clock Secondary Clock Secondary Clock Secondary Clock

Region R5C1

Region R5C2

Region R5C3

Region R5C4

SERDES

Spine Repeaters

EBR Row

Regional Boundary

2-15

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