AT90PWM81(2010) 데이터 시트보기 (PDF) - Atmel Corporation

부품명

상세내역

제조사

AT90PWM81
(Rev.:2010)

8-bit Microcontroller with 8K Bytes In-System Programmable Flash

Atmel Corporation 

There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt

flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to exe-

cute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags

can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition

occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remem-

bered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt

conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) will

be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of

priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do

not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled,

the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more

instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored

when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No inter-

rupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction.

The following example shows how this can be used to avoid interrupts during the timed EEPROM write

sequence.

Assembly Code Example

in r16, SREG ; store SREG value

cli

; disable interrupts during timed sequence

sbi EECR, EEMWE ; start EEPROM write

sbi EECR, EEWE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG;

/* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG;

/* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before

any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

14 AT90PWM81

7734P–AVR–08/10

Share Link: