AT90PWM81(2010) 데이터 시트보기 (PDF) - Atmel Corporation

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AT90PWM81
(Rev.:2010)

8-bit Microcontroller with 8K Bytes In-System Programmable Flash

Atmel Corporation 

• Bits 5..4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bit setting defines which programming action that will be triggered

when writing EEWE. It is possible to program data in one atomic operation (erase the old value and pro-

gram the new value) or to split the Erase and Write operations in two different operations. The

Programming times for the different modes are shown in Table 4-1. While EEWE is set, any write to

EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy

programming.

Table 4-1.

EEPM1

0

0

1

1

EEPROM Mode Bits

EEPM0

Programming

Time

0

3.4 ms

1

1.8 ms

0

1.8 ms

1

–

Operation

Erase and Write in one operation (Atomic Operation)

Erase Only

Write Only

Flush temporary EEPROM page buffer

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to

zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is

cleared. The interrupt will not be generated during EEPROM write or SPM.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When

EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at the selected

address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been written to one by

software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an

EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are

correctly set up, the EEWE bit must be written to one to write the value into the EEPROM. The EEMWE

bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes

place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4

is not essential):

1. Wait until EEWE becomes zero.

2. Wait until SPMEN (Store Program Memory Enable) in SPMCSR (Store Program Memory Con-

trol and Status Register) becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check

that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if

the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being

updated by the CPU, step 2 can be omitted. See “Boot Loader Support – Read-While-Write Self-Program-

ming” on page 232 for details about Boot programming.

20 AT90PWM81

7734P–AVR–08/10

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