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AT90PWM81(2010) 데이터 시트보기 (PDF) - Atmel Corporation

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AT90PWM81 Datasheet PDF : 325 Pages
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Figure 4-3. On-chip Data SRAM Access Cycles
T1
T2
T3
clk
CPU
Address
Data
WR
Data
RD
Compute Address
Address valid
Memory Access Instruction
Next Instruction
4.3 EEPROM Data Memory
The AT90PWM81 contains 512 bytes of data EEPROM memory. It is organized as a separate data space,
in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000
write/erase cycles. The access between the EEPROM and the CPU is described in the following, specify-
ing the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
For a detailed description of SPI and Parallel data downloading to the EEPROM, see “Serial Download-
ing” on page 261, and “Parallel Programming Parameters, Pin Mapping, and Commands” on page 252
respectively.
4.3.1
EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 4-2. A self-timing function, however, lets the
user software detect when the next byte can be written. If the user code contains instructions that write the
EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall
slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than
specified as minimum for the clock frequency used. For details on how to avoid problems in these situa-
tions seeSee “Preventing EEPROM Corruption” on page 25.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to
the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is exe-
cuted. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is
executed.
18 AT90PWM81
7734P–AVR–08/10

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