CS42L56-CNZ 데이터 시트보기 (PDF) - Cirrus Logic

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CS42L56-CNZ

Ultralow Power, Stereo Codec with Class H Headphone Amp

Cirrus Logic 

CS42L56

LIST OF FIGURES

Figure 1.Typical Connection Diagram - Four Pseudo-Differential Analog Inputs ...................................... 11

Figure 2.Typical Connection Diagram - Two Pseudo-Differential / Three Single-Ended Analog Inputs ... 12

Figure 3.Typical Connection Diagram - Six Single-Ended Analog Inputs ................................................. 13

Figure 4.CMRR Test Configuration ........................................................................................................... 16

Figure 5.AINxREF Input Voltage Test Configuration ................................................................................ 16

Figure 6.HP Output Test Configuration ..................................................................................................... 20

Figure 7.Line Output Test Configuration ................................................................................................... 20

Figure 8.Serial Port Timing (Slave Mode) ................................................................................................. 22

Figure 9.Serial Port Timing (Master Mode) ............................................................................................... 22

Figure 10.I²C Control Port Timing ............................................................................................................. 23

Figure 11.Control Port Timing - SPI Format .............................................................................................. 24

Figure 12.Power Consumption Test Configuration ................................................................................... 27

Figure 13.Analog Input Signal Flow .......................................................................................................... 31

Figure 14.Stereo Pseudo-Differential Input ............................................................................................... 32

Figure 15.Analog Input Attenuation ........................................................................................................... 33

Figure 16.Example Analog Input Attenuation ............................................................................................ 33

Figure 17.MIC Input Mix w/Common Mode Rejection ............................................................................... 34

Figure 18.ALC Operation .......................................................................................................................... 35

Figure 19.DSP Engine Signal Flow ........................................................................................................... 37

Figure 20.Analog Output Stage ................................................................................................................. 38

Figure 21.Class H Volume-Adapt Paths ................................................................................................... 39

Figure 22.Volume Sum Effects ................................................................................................................. 40

Figure 23.Channel/Amp Effect .................................................................................................................. 40

Figure 24.HP/Line Channel Effects ........................................................................................................... 41

Figure 25.VHPFILT Transitions ................................................................................................................. 42

Figure 26.VHPFILT Hysteresis ................................................................................................................. 43

Figure 27.Class H Power to Load vs. Power from VCP Supply - 32 W .................................................... 43

Figure 28.Class H Power to Load vs. Power from VCP Supply - 16 W .................................................... 44

Figure 29.Beep Configuration Options ...................................................................................................... 45

Figure 30.Peak Detect & Limiter ............................................................................................................... 46

Figure 31.Serial Port Timing in Master Mode ............................................................................................ 48

Figure 32.I²S Format ................................................................................................................................. 49

Figure 33.Left-Justified Format ................................................................................................................. 49

Figure 34.Control Port Timing in SPI Mode .............................................................................................. 53

Figure 35.Control Port Timing, I²C Write ................................................................................................... 54

Figure 36.Control Port Timing, I²C Read ................................................................................................... 54

Figure 37.PGA Step Size vs. Volume Setting ........................................................................................... 88

Figure 38.PGA Output Volume vs. Volume Setting .................................................................................. 88

Figure 39.HP/Line Step Size vs. Volume Setting ...................................................................................... 88

Figure 40.HP/Line Output Volume vs. Volume Setting ............................................................................. 88

Figure 41.ADC Frequency Response ....................................................................................................... 89

Figure 42.ADC Stopband Rejection .......................................................................................................... 89

Figure 43.ADC Transition Band ................................................................................................................ 89

Figure 44.ADC Transition Band Detail ...................................................................................................... 89

Figure 45.DAC Frequency Response ....................................................................................................... 89

Figure 46.DAC Stopband .......................................................................................................................... 89

Figure 47.DAC Transition Band ................................................................................................................ 89

Figure 48.DAC Transition Band (Detail) .................................................................................................... 89

DS851F2

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