UPD78F0512AGA-GAM-AX 데이터 시트보기 (PDF) - Renesas Electronics
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UPD78F0512AGA-GAM-AX Datasheet PDF : 982 Pages
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78K0/Kx2
CHAPTER 1 OUTLINE
(1) Conventional-specification products (μPD78F05xx and 78F05xxD) (3/3)
<4> When high-speed system clock (X1 oscillation or external clock input) is used and entry RAM is located
in short direct addressing range
Library Name
Self programming start library
Initialize library
Mode check library
Block blank check library
Block erase library
Word write library
Block verify library
Self programming end library
Get information library Option value: 03H
Option value: 04H
Option value: 05H
Set information library
EEPROM write library
Processing Time (μs)
Normal Model of C Compiler
Static Model of C Compiler/Assembler
Min.
Max.
Min.
Max.
34/fCPU
49/fCPU + 224.6875
35/fCPU + 113.625
29/fCPU + 113.625
174/fCPU + 6120.9375
134/fCPU + 6120.9375
174/fCPU +
174/fCPU +
134/fCPU +
134/fCPU +
30820.75
298675
30820.75
298675
318 (321)/fCPU +
383
318 (321)/fCPU +
1230.5
262 (265)/fCPU +
383
262 (265)/fCPU +
1230.5
174/fCPU + 13175.4375
34/fCPU
134/fCPU + 13175.4375
171 (172)/fCPU + 171.3125
181 (182)/fCPU + 166.75
404 (411)/fCPU + 231.875
75/fCPU +
75/fCPU +
78884.5625
527566.875
129 (130)/fCPU + 171.3125
139 (140)/fCPU + 166.75
362 (369)/fCPU + 231.875
67/fCPU +
67/fCPU +
78884.5625
527566.875
318 (321)/fCPU +
538.75
318 (321)/fCPU +
1386.25
262 (265)/fCPU +
538.75
262 (265)/fCPU +
1386.25
Remarks 1. Values in parentheses indicate values when a write start address structure is located other than in the
internal high-speed RAM.
2. The above processing times are those during stabilized operation of the internal high-speed oscillator
(RSTS = 1).
3. fCPU: CPU operation clock frequency
4. RSTS: Bit 7 of the internal oscillation mode register (RCM)
R01UH0008EJ0401 Rev.4.01
25
Jul 15, 2010
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