UPD78F0512AGA-GAM-AX 데이터 시트보기 (PDF) - Renesas Electronics

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UPD78F0512AGA-GAM-AX

8-Bit Single-Chip Microcontrollers

Renesas Electronics 

78K0/Kx2

CHAPTER 1 OUTLINE

1.1.6 Interrupt response time for self programming library

(1) Conventional-specification products (μPD78F05xx and 78F05xxD) (1/2)

<1> When internal high-speed oscillation clock is used

Library Name

Block blank check library

Block erase library

Word write library

Block verify library

Set information library

EEPROM write library

Interrupt Response Time (μs (Max.))

Normal Model of C Compiler

Static Model of C Compiler/Assembler

Entry RAM location

is outside short

direct addressing

range

Entry RAM location

is in short direct

addressing range

Entry RAM location

is outside short

direct addressing

range

Entry RAM location

is in short direct

addressing range

933.6

668.6

927.9

662.9

1026.6

763.6

1020.9

757.9

2505.8

1942.8

2497.8

1934.8

958.6

693.6

952.9

687.9

476.5

211.5

475.5

210.5

2760.8

2168.8

2759.5

2167.5

Remarks 1. The above interrupt response times are those during stabilized operation of the internal high-speed

oscillator (RSTS = 1).

2. RSTS: Bit 7 of the internal oscillation mode register (RCM)

<2> When high-speed system clock is used (normal model of C compiler)

Library Name

Block blank check library

Block erase library

Word write library

Block verify library

Set information library

EEPROM write libraryNote

Interrupt Response Time (μs (Max.))

RSTOP = 0, RSTS = 1

RSTOP = 1

Entry RAM location

is outside short

direct addressing

range

Entry RAM location

is in short direct

addressing range

Entry RAM location

is outside short

direct addressing

range

Entry RAM location

is in short direct

addressing range

179/fCPU + 507

179/fCPU + 559

333/fCPU + 1589

179/fCPU + 518

80/fCPU + 370

29/fCPU + 1759

179/fCPU + 407

179/fCPU + 460

333/fCPU + 1298

179/fCPU + 418

80/fCPU + 165

29/fCPU + 1468

179/fCPU + 1650

179/fCPU + 1702

333/fCPU + 2732

179/fCPU + 1661

80/fCPU + 1513

29/fCPU + 1759

179/fCPU + 714

179/fCPU + 767

333/fCPU + 1605

179/fCPU + 725

80/fCPU + 472

29/fCPU + 1468

333/fCPU + 834

333/fCPU + 512

333/fCPU + 2061

333/fCPU + 873

Note The longer value of the EEPROM write library interrupt response time becomes the Max. value, depending on

the value of fCPU.

Remarks 1. fCPU: CPU operation clock frequency

2. RSTOP: Bit 0 of the internal oscillation mode register (RCM)

3. RSTS: Bit 7 of the internal oscillation mode register (RCM)

R01UH0008EJ0401 Rev.4.01

29

Jul 15, 2010

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