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LT3796

100V Constant-Current and Constant-Voltage Controller with Dual Current Sense

Linear Technology 

LT3796

PIN FUNCTIONS

SYNC (Pin 13): The SYNC pin is used to synchronize the

internal oscillator to an external logic level signal. If SYNC

is used, the RT resistor should be chosen to program an

internal switching frequency 20% slower than the SYNC

pulse frequency. Gate turn-on occurs a fixed delay after

the rising edge of SYNC. Use a 50% duty cycle waveform

to drive this pin. If not used, tie this pin to GND.

PWM (Pin 14): PWM Input Signal Pin. A signal low turns

off switching, idles the oscillator, disconnects the VC pin

from all internal loads, and makes the TG pin high.

FAULT (Pin 15): An open-collector pull-down on FAULT

asserts when any of the following conditions happen: 1.

FB1 overvoltage (VFB1 > 1.3V), 2. INTVCC undervoltage,

3. LED overcurrent (V(ISP-ISN) > 375mV), or 4. Thermal

shutdown. If all faults are removed, FAULT flag returns

high. Fault status is only updated during PWM high

state and latched during PWM low state. FAULT remains

asserted until the SS pin is discharged below 0.2V for

cases 2, 3 and 4 above.

VMODE (Pin 16): An open-collector pull-down on VMODE

asserts if the FB1 input is above 1.19V (typical), and

V(ISP-ISN) is less than 25mV (typical). To function, the

pin requires an external pull-up resistor. VMODE status is

updated only during PWM high state and latched during

PWM low state.

SENSE (Pin 18): The current sense input for the control

loop. Kelvin connect this pin to the positive terminal of

the switch current sense resistor, RSENSE, in the source

of the N-channel MOSFET. The negative terminal of the

current sense resistor should be Kelvin connected to the

GND plane of the IC.

GATE (Pin 19): N-Channel MOSFET Gate Driver Output.

Switches between INTVCC and GND. It is driven to GND

during shutdown, fault or idle states.

INTVCC (Pin 20): Regulated Supply for Internal Loads, GATE

Driver and Top Gate (PMOS) Driver. Supplied from VIN and

regulates to 7.7V (typical). INTVCC must be bypassed with

a 4.7μF capacitor placed close to the pin. Connect INTVCC

directly to VIN if VIN is always less than or equal to 7V.

VIN (Pin 23): Input Supply Pin. Must be locally bypassed

with a 0.22μF (or larger) capacitor placed close to the IC.

EN/UVLO (Pin 24): Enable and Undervoltage Lockout

Pin. An accurate 1.22V falling threshold with externally

programmable hysteresis detects when power is OK to

enable switching. Rising hysteresis is generated by the

external resistor divider and an accurate internal 3μA

pull-down current. Above the threshold (but below 6V),

EN/UVLO input bias current is sub-μA. Below the falling

threshold, a 3μA pull-down current is enabled so the

user can define the hysteresis with the external resistor

selection. An undervoltage condition resets soft-start.

Tie to 0.4V, or less, to disable the device and reduce VIN

quiescent current below 1μA.

VS (Pin 25): Current Sense Amplifier Power Supply Pin.

This pin supply current to the current sense amplifier and

can operate from 3V to 100V.

CSN (Pin 26): Negative Current Sense Input Terminal.

CSN remains functional for voltages up to 100V. Typically

connected to VS and CSP as shown in Figure 9.

CSP (Pin 27): Positive Current Sense Input Terminal. The

internal sense amplifier sinks current from CSP to regulate

it to the same potential as CSN. A resistor (RIN1) tied from

VIN to CSP sets the output current ICSOUT = VSNS/RIN1.

VSNS is the voltage developed across RSNS. See Figure 9.

CSOUT (Pin 28): Current Sense Amplifier Output. CSOUT

pin sources the current that is drawn from CSP. Typically

is output to an external resistor to GND.

3796f

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