MFRC522_(2007) 데이터 시트보기 (PDF) - NXP Semiconductors.
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MFRC522_ Datasheet PDF : 109 Pages
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NXP Semiconductors
MFRC522
Contactless Reader IC
9.2.1.10 FIFODataReg
In- and output of 64 byte FIFO buffer.
Table 25: FIFODataReg register (address 09h); reset value: XXh
Bit
7
6
5
4
3
2
1
0
Symbol
FIFOData
Access
dy
Rights
Table 26: Description ofFIFODataReg bits
Bit
Symbol
Description
7 to 0 FIFOData
Data input and output port for the internal 64 byte FIFO buffer. The
FIFO buffer acts as parallel in/parallel out converter for all serial data
stream in- and outputs.
9.2.1.11 FIFOLevelReg
Indicates the number of bytes stored in the FIFO.
Table 27: FIFOLevelReg register (address 0Ah); reset value: 00h
Bit
7
6
5
4
3
2
1
0
Symbol FlushBuffer
FIFOLevel
Access
w
r
Rights
Table 28: Description of FIFOLevelReg bits
Bit
Symbol
Description
7
FlushBuffer Set to logic 1, this bit clears the internal FIFO-buffer’s read- and
write-pointer and the bit BufferOvfl in the register ErrReg immediately.
Reading this bit will always return 0.
6 to 0
FIFOLevel
Indicates the number of bytes stored in the FIFO buffer. Writing to the
FIFODataReg increments, reading decrements the FIFOLevel.
9.2.1.12 WaterLevelReg
Defines the level for FIFO under- and overflow warning.
Table 29: WaterLevelReg register (address 0Bh); reset value: 08h
Bit
7
6
5
4
3
2
1
0
Symbol
-
WaterLevel
Access
RFU
r/w
Rights
112132
Product data sheet
Rev. 3.2 — 22 May 2007
© NXP B.V. 2007. All rights reserved.
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