LTC1142(RevC) 데이터 시트보기 (PDF) - Linear Technology
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LTC1142 Datasheet PDF : 20 Pages
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LTC1142/LTC1142L/LTC1142HV
UU W U
APPLICATIO S I FOR ATIO
Figure 5 shows how the efficiency losses in one section of
a typical LTC1142 regulator end up being apportioned.
The gate charge loss is responsible for the majority of the
efficiency lost in the mid-current region. If Burst Mode
operation was not employed at low currents, the gate
charge loss alone would cause efficiency to drop to
unacceptable levels. With Burst Mode operation, the DC
supply current represents the lone (and unavoidable) loss
component which continues to become a higher percent-
age as output current is reduced. As expected, the I2R
losses dominate at high load currents.
Other losses including CIN and COUT ESR dissipative
losses, MOSFET switching losses, Schottky conduction
losses during dead-time and inductor core losses, gener-
ally account for less than 2% total additional loss.
100
I2R
GATE CHARGE
95
1/2 LTC1142 IQ
90
85
80
0.01
0.03 0.1
0.3
1
OUTPUT CURRENT (A)
3
1142 F05
Figure 5. Efficiency Loss
Design Example
As a design example, assume VIN = 12V (nominal), 5V
section, IMAX = 2A and f = 200kHz; RSENSE, CT and L can
immediately be calculated:
RSENSE = 100mV/2 = 0.05Ω
tOFF = (1/200kHz) × [1 – (5/12)] = 2.92µs
CT5 = 2.92µs/(1.3 × 104) = 220pF
L2MIN = 5.1 × 105 × 0.05Ω × 220pF × 5V = 28µH
Assume that the MOSFET dissipations are to be limited to
PN = PP = 250mW.
If TA = 50°C and the thermal resistance of each MOSFET
is 50°C/ W, then the junction temperatures will be 63°C
and δP = δN = 0.007(63 – 25) = 0.27. The required RDS(ON)
for each MOSFET can now be calculated:
P
-
Ch
RDS(ON)
=
12(0.25)
5(2)2(1.27)
=
0.12Ω
N
-
Ch
RDS(ON)
=
12(0.25)
5(2)2(1.27)
=
0.085Ω
The P-channel requirement can be met by a Si9430DY,
while the N-channel requirement is exceeded by a
Si9410DY. Note that the most stringent requirement for
the N-channel MOSFET is with VOUT = 0 (i.e., short circuit).
During a continuous short circuit, the worst case
N-channel dissipation rises to:
PN = ISC(AVG)2 × RDS(ON) × (1 + δN)
With the 0.05Ω sense resistor, ISC(AVG) = 2A will result,
increasing the 0.085Ω N-channel dissipation to 450mW at
a die temperature of 73°C.
CIN will require an RMS current rating of at least 1A at
temperature, and COUT will require an ESR of 0.05Ω for
optimum efficiency.
Now allow VIN to drop to its minimum value. At lower input
voltages the operating frequency will decrease and the
P-channel will be conducting most of the time, causing its
power dissipation to increase. At VIN(MIN) = 7V:
fMIN = (1/2.92µs)[1 – (5V/ 7V)] = 98kHz
PP
=
5V(0.12Ω)(2A)2(1.27)
7V
=
435mV
A similar calculation for the 3.3V section results in the
component values shown in Figure 14.
LTC1142HV-ADJ/LTC1142L-ADJ
Adjustable Applications
When an output voltage other than 3.3V or 5V is required,
the LTC1142 adjustable version is used with an external
resistive divider from VOUT to VFB, Pin 2 (16). The regu-
lated output voltage is determined by:
VOUT
=
1.25
1
+
R2
R1
14
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