LTC1142(RevC) 데이터 시트보기 (PDF) - Linear Technology
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LTC1142 Datasheet PDF : 20 Pages
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UU W U
APPLICATIO S I FOR ATIO
To prevent stray pickup a 100pF capacitor is suggested
across R1 located close to the LTC1142HV-ADJ/LTC1142L-
ADJ as in Figure 6. The external divider network must be
placed across COUT with the negative plate of COUT returned
to signal ground. Refer to the Board Layout Checklist.
VFB
[PIN 2(16)]
SGND
[PIN 4(18)]
100pF
R2
R1
RSENSE
+
VOUT
COUT
1142 F06
Figure 6. LTC1142-ADJ External Feedback Network
Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1142/LTC1142L/LTC1142HV
LTC1142. These items are also illustrated graphically in
the layout diagram of Figure 7. In general each block
should be self-contained with little cross coupling for best
performance. Check the following in your layout:
1. Are the signal and power grounds segregated? The
LTC1142 signalground[Pin 3 (17) for the LTC1142, Pin
4 (18) for LTC1142-ADJ] must return to the (–) plate of
COUT. The power ground returns to the source of the
N-channel MOSFET, anode of the Schottky diode,
and (–) plate of CIN, which should have as short lead
lengths as possible.
2. Does the LTC1142 Sense – , Pin 28 (14) connect to a
point close to RSENSE and the (+) plate of COUT?
3. Are the Sense – and Sense + leads routed together with
minimum PC trace spacing? The 1000pF capacitor
+
RSENSE3
VOUT3
–
–
VIN3
+
1000pF
COUT3
SHUTDOWN (3.3V OUTPUT)
1 SENSE +3
2
SHUTDOWN 3
SENSE –3 28
27
ITH3
3300pF
1k
CT3
3 SGND3
26
L1
INT VCC3
4
PGND3
25
CT3
5 NC
24
VIN3
VIN3
P-CH
+
N-CH
6
NDRIVE 3
PDRIVE 3 23
1µF
D2
7 NC
NC 22
D1
8 NC
LTC1142
NC 21
P-CH
CIN3
1µF +
9 PDRIVE 5
20
NDRIVE 5
VIN5
10
VIN5
NC 19
N-CH
11
18
CT5
PGND5
L2
12
17
3300pF
INT VCC5
SGND5
CT5
13
16
ITH5
SHUTDOWN 5
SHUTDOWN (5V OUTPUT)
1k
14 SENSE–5
SENSE+5 15
COUT5 +
BOLD LINES INDICATE HIGH CURRENT PATHS
1000pF
Figure 7. LTC1142 Layout Diagram (see Board Layout Checklist)
+
CIN5
VIN5
–
–
VOUT5
RSENSE5
+
1142 F07
15
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