MT9300B 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT9300B

Multi-Channel Voice Echo Canceller

Zarlink Semiconductor Inc 

MT9300B

Data Sheet

Serial Data Interface Timing

The MT9300B provides ST-BUS and GCI interface timing. The Serial Interface clock frequency, C4i, is 4.096 MHz.

The input and output data rate of the ST-Bus and GCI bus is 2.048 Mb/s.

The 8 KHz input frame pulse can be in either ST-BUS or GCI format. The MT9300B automatically detects the

presence of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS format, every second falling

edge of the C4i clock marks a bit boundary, and the data is clocked in on the rising edge of C4i, three quarters of

the way into the bit cell (See Figure 10). In GCI format, every second rising edge of the C4i clock marks the bit

boundary, and data is clocked in on the second falling edge of C4i, half the way into the bit cell (see Figure 11).

Base

Addr + Echo Canceller A

00h Control Reg A1

01h Control Reg A2

02h Status Reg

03h Reserved

04h Flat Delay Reg

05h Reserved

06h Decay Step Size Reg

07h Decay Step Number

08h Control Reg A3

09h Reserved

0Ah Reserved

0Bh Reserved

0Ch Rin Peak Detect Reg

0Eh Sin Peak Detect Reg

10h Error Peak Detect Reg

12h Reserved

14h DTDT Reg

16h Reserved

18h NLPTHR

1Ah Step Size, MU

1Ch Reserved

1Eh Reserved

Base

Addr + Echo Canceller B

20h Control Reg B1

21h Control Reg B2

22h Status Reg

23h Reserved

24h Flat Delay Reg

25h Reserved

26h Decay Step Size Reg

27h Decay Step Number

28h Control Reg B3

29h Reserved

2Ah Reserved

2Bh Reserved

2Ch Rin Peak Detect Reg

2Eh Sin Peak Detect Reg

30h Error Peak Detect Reg

32h Reserved

34h DTDT Reg

36h Reserved

38h NLPTHR

3Ah Step Size, MU

3Ch Reserved

3Eh Reserved

Figure 8 - Memory Mapping of per channel Control and Status Registers

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Zarlink Semiconductor Inc.

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