MT9300B 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
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MT9300B Datasheet PDF : 39 Pages
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MT9300B
Data Sheet
Memory Mapped Control and Status registers
Internal memory and registers are memory mapped into the address space of the HOST interface. The internal dual
ported memory is mapped into segments on a “per channel” basis to monitor and control each individual echo
canceller and associated PCM channels. For example, in Normal configuration, echo canceller #5 makes use of
Echo Canceller B from group 2. It occupies the internal address space from 0A0h to 0BFh and interfaces to PCM
channel #5 on all serial PCM I/O streams.
As illustrated in Figure 8, the “per channel” registers provide independent control and status bits for each echo canceller.
Figure 9 shows the memory map of the control/status register blocks for all echo cancellers.
Group 0
Echo
Cancellers
Registers
Channel 0, EC A Ctrl/Stat Registers
Channel 1, EC B Ctrl/Stat Registers
Group 1
Echo
Cancellers
Registers
Channel 2, EC A Ctrl/Stat Registers
Channel 3, EC B Ctrl/Stat Registers
Groups 2 --> 14
Echo Cancellers
Registers
0000H --> 001FH
0020H --> 003FH
0040H --> 005FH
0060H --> 007FH
Group 15
Echo
Cancellers
Registers
Channel 30, EC A Ctrl/Stat Registers
Channel 31, EC B Ctrl/Stat Registers
Main Control Registers <15:0>
Interrupt FIFO Register
Test Register
03C0H --> 03DFH
03E0H --> 03FFH
0400H --> 040FH
0410H
0411H
Figure 9 - Memory Mapping
When Extended Delay or Back-to-Back configuration is selected, Control Register A1/B1 and Control Register 2
of the selected group of echo cancellers require special care. Refer to the Register description section.
Table 2 is a list of the channels used for the 16 groups of echo cancellers when they are configured as Extended
Delay or Back-to-Back
Normal Configuration
For a given group (group 0 to 15), 2 PCM I/O channels are used. For example, group 1 Echo Cancellers A and B,
channels 2 and 3 are active.
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