MC68334GVFC16 데이터 시트보기 (PDF) - Freescale Semiconductor

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MC68334GVFC16

32-Bit Modular Microcontroller

Freescale Semiconductor 

2.5 Signal Function

Table 6 MCU Signal Function

Mnemonic

ADDR[23:0]

AN[6:0]

AS

AVEC

BERR

BG

BGACK

BKPT

BR

CLKOUT

CS[10:0]

CSBOOT

DATA[15:0]

DS

DSACK[1:0]

DSI, DSO, DSCLK

ECLK

EXTAL, XTAL

FC[2:0]

FREEZE

HALT

IFETCH

IPIPE

IRQ[7:1]

MODCLK

PADA[6:0]

PC[6:0]

PE[7:0]

PF[7:0]

QUOT

RESET

RMC

R/W

SIZ[1:0]

TPUCH[15:0]

TSC

T2CLK

VRH, VRL

XFC

Signal Name

Function

Address Bus

ADC Analog Input

Address Strobe

Autovector

Bus Error

24-bit address bus used by CPU32

Inputs to ADC multiplexer

Indicates that a valid address is on the address bus

Requests an automatic vector during interrupt acknowledge

Indicates that a bus error has occurred

Bus Grant

Indicates that the MCU has relinquished the bus

Bus Grant Acknowledge Indicates that an external device has assumed bus mastership

Breakpoint

Signals a hardware breakpoint to the CPU

Bus Request

System Clockout

Chip Selects

Boot Chip Select

Data Bus

Data Strobe

Data and Size

Acknowledge

Indicates that an external device requires bus mastership

System clock output

Select external devices at programmed addresses

Chip select for external boot start-up ROM

16-bit data bus

During a read cycle, indicates when it is possible for an external

device to place data on the data bus. During a write cycle,

indicates that valid data is on the data bus.

Provide asynchronous data transfers and dynamic bus sizing

Development Serial In,

Out, Clock

E-Clock

Crystal Oscillator

Function Codes

Serial I/O and clock for background debugging mode

External M6800 bus clock output

Connections for clock synthesizer circuit reference;

a crystal or an external oscillator can be used

Identify processor state and current address space

Freeze

Indicates that the CPU has entered background mode

Halt

Suspend external bus activity

Instruction Fetch

Identifies bus cycles in which operand is loaded into pipeline

Instruction Pipeline

Interrupt Request Level

Clock Mode Select

Port ADA

Port C

Port E

Indicates instruction pipeline activity

Provide prioritized interrupts to the CPU

Selects the source and type of system clock

ADC digital input port signals

SIM digital output port signals

SIM digital I/O port signals

Port F

SIM digital I/O port signals

Quotient Out

Provides the quotient bit of the polynomial divider

Reset

System reset

Read-Modify-Write Cycle Indicates an indivisible read-modify-write instruction

Read/Write

Indicates the direction of data transfer on the bus

Size

Indicates the number of bytes to be transferred during a bus cycle

TPU I/O Channels Bidirectional TPU channels

Three-State Control Places all output drivers in a high-impedance state

TCR2 Clock

TPU clock input

ADC Reference Voltage Provide precise reference for A/D conversion

External Filter Capacitor Connection for external phase-locked loop filter capacitor

MC68334

10

MC68334TS/D

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