AT91M40800(2002) 데이터 시트보기 (PDF) - Atmel Corporation

부품명

상세내역

제조사

AT91M40800
(Rev.:2002)

AT91 ARM® Thumb® Microcontrollers

Atmel Corporation 

AT91M40800

Peripherals

Peripheral Registers

Peripheral Interrupt Control

Peripheral Data Controller

The AT91M40800 microcontroller peripherals are connected to the 32-bit wide

Advanced Peripheral Bus. Peripheral registers are only word accessible – byte and half-

word accesses are not supported. If a byte or a half-word access is attempted, the mem-

ory controller automatically masks the lowest address bits and generates an word

access.

Each peripheral has a 16-Kbyte address space allocated (the AIC only has a 4-Kbyte

address space).

The following registers are common to all peripherals:

• Control Register – write only register that triggers a command when a one is written

to the corresponding position at the appropriate address. Writing a zero has no

effect.

• Mode Register – read/write register that defines the configuration of the peripheral.

Usually has a value of 0x0 after a reset.

• Data Registers – read and/or write register that enables the exchange of data

between the processor and the peripheral.

• Status Register – read only register that returns the status of the peripheral.

• Enable/Disable/Status Registers are shadow command registers. Writing a one in

the Enable Register sets the corresponding bit in the Status Register. Writing a one

in the Disable Register resets the corresponding bit and the result can be read in the

Status Register. Writing a bit to zero has no effect. This register access method

maximizes the efficiency of bit manipulation, and enables modification of a register

with a single non-interruptible instruction, replacing the costly read-modify-write

operation.

Unused bits in the peripheral registers are shown as “–” and must be written at 0 for

upward compatibility. These bits read 0.

The Interrupt Control of each peripheral is controlled from the status register using the

interrupt mask. The status register bits are ANDed to their corresponding interrupt mask

bits and the result is then ORed to generate the Interrupt Source signal to the Advanced

Interrupt Controller.

The interrupt mask is read in the Interrupt Mask Register and is modified with the Inter-

rupt Enable Register and the Interrupt Disable Register. The enable/disable/status (or

mask) makes it possible to enable or disable peripheral interrupt sources with a non-

interruptible single instruction. This eliminates the need for interrupt masking at the AIC

or Core level in real-time and multi-tasking systems.

The AT91M40800 microcontroller has a 4-channel PDC dedicated to the two on-chip

USARTs. One PDC channel is dedicated to the receiver and one to the transmitter of

each USART.

The user interface of a PDC channel is integrated in the memory space of each USART.

It contains a 32-bit Address Pointer Register (RPR or TPR) and a 16-bit Transfer

Counter Register (RCR or TCR). When the programmed number of transfers are per-

formed, a status bit indicating the end of transfer is set in the USART Status Register

and an interrupt can be generated.

11

1348DS–ATARM–02/02

Share Link: