ADSP-BF538(Rev0) 데이터 시트보기 (PDF) - Analog Devices
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ADSP-BF538 Datasheet PDF : 56 Pages
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event service routines to be active simultaneously. Prioritization
ensures that servicing of a higher priority event takes prece-
dence over servicing of a lower priority event. The controller
provides support for five different types of events:
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
• Reset – This event resets the processor.
• Nonmaskable interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut-
down of the system.
• Exceptions – Events that occur synchronously to program
flow (the exception is taken before the instruction is
allowed to complete). Conditions such as data alignment
violations and undefined instructions cause exceptions.
• Interrupts – Events that occur asynchronously to program
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processors is saved on the
supervisor stack.
The ADSP-BF538/ADSP-BF538F processor’s event controllers
consist of two stages, the core event controller (CEC) and the
system interrupt controllers (SIC). The core event controller
works with the system interrupt controllers to prioritize and
control all system events. Conceptually, interrupts from the
peripherals enter into one of the SICs, and are then routed
directly into the general-purpose interrupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority inter-
rupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of the processor.
Table 2 describes the inputs to the CEC, identifies their names
in the event vector table (EVT), and lists their priorities.
ADSP-BF538/ADSP-BF538F
Table 2. Core Event Controller (CEC)
Priority
(0 is Highest) Event Class
0
Emulation/Test Control
1
Reset
2
Nonmaskable Interrupt
3
Exception
4
Reserved
5
Hardware Error
6
Core Timer
7
General Interrupt 7
8
General Interrupt 8
9
General Interrupt 9
10
General Interrupt 10
11
General Interrupt 11
12
General Interrupt 12
13
General Interrupt 13
14
General Interrupt 14
15
General Interrupt 15
EVT Entry
EMU
RST
NMI
EVX
—
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
Rev. 0 | Page 7 of 56 | May 2007
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