ADSP-BF538(Rev0) 데이터 시트보기 (PDF) - Analog Devices
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ADSP-BF538 Datasheet PDF : 56 Pages
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GENERAL DESCRIPTION
The ADSP-BF538/ADSP-BF538F processors are members of
the Blackfin family of products, incorporating the Analog
Devices Inc./Intel Micro Signal Architecture (MSA). Blackfin
processors combine a dual-MAC state-of-the-art signal process-
ing engine, the advantages of a clean, orthogonal RISC-like
microprocessor instruction set, and single-instruction, multi-
ple-data (SIMD) multimedia capabilities into a single
instruction set architecture.
The ADSP-BF538/ADSP-BF538F processors are completely
code compatible with other Blackfin processors, differing only
with respect to performance, peripherals, and on-chip memory.
Specific performance, peripherals, and memory configurations
are shown in Table 1.
Table 1. Processor Features
Feature
ADSP-
BF538
ADSP-
BF538F4
SPORTs
4
4
UARTs
3
3
SPI
3
3
TWI
2
2
PPI
1
1
CAN
1
1
Instruction SRAM/Cache 16K bytes 16K bytes
Instruction SRAM
64K bytes 64K bytes
Data SRAM/Cache
32K bytes 32K bytes
Data SRAM
32K bytes 32K bytes
Scratchpad
4K bytes 4K bytes
Flash
Not
256K ϫ 16-
Applicable bit
Maximum Speed Grade 533 MHz
1066
MMACS
533 MHz
1066
MMACS
Package Option
BC-316 BC-316
ADSP-
BF538F8
4
3
3
2
1
1
16K bytes
64K bytes
32K bytes
32K bytes
4K bytes
512K ϫ 16-
bit
533 MHz
1066
MMACS
BC-316
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next generation applications that require RISC-like program-
mability, multimedia support and leading edge signal
processing in one integrated package.
LOW POWER ARCHITECTURE
Blackfin processors provide world class power management and
performance. They are designed using a low power and low
voltage methodology and feature dynamic power management
which is the ability to vary both the voltage and frequency of
operation to significantly lower overall power consumption.
Varying the voltage and frequency can result in a substantial
reduction in power consumption, compared with just varying
the frequency of operation. This translates into longer battery
life and lower heat dissipation.
ADSP-BF538/ADSP-BF538F
SYSTEM INTEGRATION
The ADSP-BF538/ADSP-BF538F processors are highly inte-
grated system-on-a-chip solutions for the next generation of
consumer and industrial applications including audio and video
signal processing. By combining advanced memory configura-
tions, such as on-chip flash memory, industry-standard
interfaces, and a high performance signal processing core, cost-
effective solutions can be quickly developed, without the need
for costly external components. The system peripherals include
three UART ports, three SPI ports, four serial ports (SPORTs),
one CAN interface, two 2-wire interfaces (TWI), four general-
purpose timers (three with PWM capability), a real-time clock, a
watchdog timer, a parallel peripheral interface (PPI), and gen-
eral-purpose I/O pins.
ADSP-BF538/ADSP-BF538F PROCESSOR
PERIPHERALS
The ADSP-BF538/ADSP-BF538F processors contain a rich set
of peripherals connected to the core via several high bandwidth
buses, providing flexibility in system configuration as well as
excellent overall system performance (see the block diagram
on Page 1). The general-purpose peripherals include functions
such as UART, timers with PWM (pulse-width modulation)
and pulse measurement capability, general-purpose I/O pins, a
real time clock, and a watchdog timer. This set of functions sat-
isfies a wide variety of typical system support needs and is
augmented by the system expansion capabilities of the device. In
addition to these general-purpose peripherals, the processors
contain high speed serial and parallel ports for interfacing to a
variety of audio, video, and modem codec functions. A CAN
2.0B controller is provided for automotive and industrial con-
trol networks. An interrupt controller manages interrupts from
the on-chip peripherals or from external sources. Power man-
agement control functions tailor the performance and power
characteristics of the processors and system to many application
scenarios.
All of the peripherals, except for general-purpose I/O, CAN,
TWI, real time clock, and timers, are supported by a flexible
DMA structure. There are also four separate memory DMA
channels dedicated to data transfers between the processor’s
various memory spaces, including external SDRAM and asyn-
chronous memory. Multiple on-chip buses running at up to
133 MHz provide enough bandwidth to keep the processor core
running with activity on all of the on-chip and external
peripherals.
The ADSP-BF538/ADSP-BF538F processors include an on-chip
voltage regulator in support of the processor’s dynamic power
management capability. The voltage regulator provides a range
of core voltage levels from a single 2.25 V to 3.6 V input. The
voltage regulator can be bypassed as needed.
Rev. 0 | Page 3 of 56 | May 2007
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