ATC35 데이터 시트보기 (PDF) - Atmel Corporation
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ATC35 Datasheet PDF : 14 Pages
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Compiled FIFO
Megacells
ATC35 Summary
A compiled FIFO (first-in first-out data flow) megacell is implemented as a soft macro
built around a Dual-Port RAM.
The compiled FIFO is a buffer memory that allows access to its memory cells by two
independent ports. The read port is referred to as port A, the write port is labelled port B.
Both ports are controlled by independent clock signals and contain address counters
which are incremented during every clock cycle.
The FIFO block makes use of a compiled Dual-Port RAM with the configuration port A
read-only and port B write-only.
Number of rows: 2, ...128 in increments of 2
Number of words: 8, 16, 32, ...16384
Bits per word: 1, ...64
Total size:
8, ...16384
The word lengths of both ports may be different, but their ratio must be one of (1, 2, 4, 8,
16, 32 or 64).
The following is a list of pins which will be found on the symbol of a module:
• CKOUT is the clock input for port A (read port).
• CKIN is the clock input for port B (write port).
• DIN<0:i-1> Data input lines.
• DOUT<0:i-1> Data output lines.
• RESETZ The clear signal.
• EMPTY The empty flag.
• FULL The full flag.
• Supply (VDD) and ground (GND).
The following table shows the estimated range of performance for particular FIFO con-
figurations, without BIST, and without output load. Access time (tACC) and cycle time
(tCYC) refer to Max industrial conditions, whereas Dynamic Power dissipation refers to
typical conditions. All examples have the same configuration for both port A and port B,
with Read/Write capability. There is no additional flag.
Word Size
Word Depth
Rows x Columns
Width (mm)
Height (mm)
Access Time (tACC) (nsec)
Cycle Time (tCYC) (nsec)
Dynamic Power (mW/MHz)
4
16
8x8
0.235
0.169
2.72
4.55
0.10
8
32
16 x 16
0.307
0.227
2.91
4.86
0.15
16
64
32 x 32
0.455
0.342
3.27
5.38
0.31
32
128
64 x 64
0.724
0.573
3.97
5.89
0.80
64
256
128 x 128
1.267
1.035
5.37
7.56
2.58
11
1063CS–CBIC–01/03
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