HT48R10A-1 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT48R10A-1

I/O Type 8-Bit MCU

Holtek Semiconductor 

HT48R10A-1/HT48C10-1

S y s te m C lo c k /4

R TC O SC

W DT

O SC

O p tio n

S e le c t

8 - b it C o u n te r

W D T P r e s c a le r

7 - b it C o u n te r

8 -to -1 M U X

W S 0~W S 2

W D T T im e - o u t

Watchdog Timer

Once the internal WDT oscillator (RC oscillator with a

period of 65ms@5V normally) is selected, it is first di-

vided by 256 (8-stage) to get the nominal time-out pe-

riod of approximately 17ms@5V. This time-out period

may vary with temperatures, VDD and process varia-

tions. By invoking the WDT prescaler, longer time-out

periods can be realized. Writing data to WS2, WS1,

WS0 (bit 2,1,0 of the WDTS) can give different time-out

periods. If WS2, WS1, and WS0 are all equal to 1, the divi-

sion ratio is up to 1:128, and the maximum time-out period

is 2.1s@5V seconds. If the WDT oscillator is disabled, the

WDT clock may still come from the instruction clock and

operate in the same manner except that in the HALT state

the WDT may stop counting and lose its protecting pur-

pose. In this situation the logic can only be restarted by ex-

ternal logic. The high nibble and bit 3 of the WDTS are

reserved for user's defined flags, which can be used to in-

dicate some specified status.

If the device operates in a noisy environment, using the

on-chip RC oscillator (WDT OSC) or 32kHz crystal oscilla-

tor (RTC OSC) is strongly recommended, since the HALT

will stop the system clock.

WS2 WS1 WS0

Division Ratio

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

1:1

1:2

1:4

1:8

1:16

1:32

1:64

1:128

WDTS (09H) Register

The WDT overflow under normal operation will initialize

²chip reset² and set the status bit ²TO². But in the HALT

mode, the overflow will initialize a ²warm reset² and only

the Program Counter and SP are reset to zero. To clear

the contents of WDT (including the WDT prescaler),

three methods are adopted; external reset (a low level to

RES), software instruction and a ²HALT² instruction.

The software instruction include ²CLR WDT² and the

other set - ²CLR WDT1² and ²CLR WDT2². Of these

two types of instruction, only one can be active depend-

ing on the option - ²CLR WDT times selection option². If

the ²CLR WDT² is selected (i.e. CLRWDT times equal

one), any execution of the ²CLR WDT² instruction will

clear the WDT. In the case that ²CLR WDT1² and ²CLR

WDT2² are chosen (i.e. CLRWDT times equal two),

these two instructions must be executed to clear the

WDT; otherwise, the WDT may reset the chip as a result

of time-out.

Power Down Operation - HALT

The HALT mode is initialized by the ²HALT² instruction

and results in the following.

· The system oscillator will be turned off but the WDT

oscillator keeps running (if the WDT oscillator is se-

lected).

· The contents of the on chip RAM and registers remain

unchanged.

· WDT and WDT prescaler will be cleared and re-

counted again (if the WDT clock is from the WDT os-

cillator).

· All of the I/O ports maintain their original status.

· The PDF flag is set and the TO flag is cleared.

The system can leave the HALT mode by means of an

external reset, an interrupt, an external falling edge sig-

nal on port A or a WDT overflow. An external reset

causes a device initialization and the WDT overflow per-

forms a ²warm reset². After the TO and PDF flags are

examined, the reason for chip reset can be determined.

The PDF flag is cleared by system power-up or execut-

ing the ²CLR² WDT instruction and is set when execut-

ing the ²HALT² instruction. The TO flag is set if the WDT

time-out occurs, and causes a wake-up that only resets

the Program Counter and SP; the others keep their orig-

inal status.

The port A wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Each bit

in port A can be independently selected to wake up the

device by the options. Awakening from an I/O port stim-

ulus, the program will resume execution of the next in-

struction. If it is awakening from an interrupt, two

sequences may happen. If the related interrupt is dis-

abled or the interrupt is enabled but the stack is full, the

program will resume execution at the next instruction. If

the interrupt is enabled and the stack is not full, the regu-

lar interrupt response takes place. If an interrupt request

flag is set to ²1² before entering the HALT mode, the

wake-up function of the related interrupt will be disabled.

Once a wake-up event occurs, it takes 1024 tSYS (sys-

tem clock period) to resume normal operation. In other

Rev. 1.90

11

November 4, 2005

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